公开(公告)号：US10171100B2

公开(公告)日：2019-01-01

申请号：US16031753

申请日：2018-07-10

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Chandrajit Debnath ,  Pratap Narayan Singh

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/08 ,  H03M1/44 ,  H03M1/16 ,  H03M1/38 ,  H03M1/10

Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

公开(公告)号：US10128835B2

公开(公告)日：2018-11-13

申请号：US15437286

申请日：2017-02-20

Applicant: STMicroelectronics International N.V.

Inventor： Prashant Singh

IPC: H03K17/687

Abstract: An integrated circuit includes an IO node, and an IO driver coupled thereto. The IO driver has a first driving circuit with a first PMOS transistor having a source coupled to a supply node and a gate coupled to receive a PMOS driving signal, and a first NMOS transistor having a source coupled to ground, a drain coupled to the drain of the first PMOS transistor, and a gate coupled to receive a NMOS driving signal. The IO driver also has a second driving circuit with a second PMOS transistor having a source coupled to the supply node and a gate coupled to receive a first delayed version of the PMOS driving signal, and a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor, a source coupled to ground, and a gate coupled to receive a first delayed version of the NMOS driving signal.

公开(公告)号：US10094876B2

公开(公告)日：2018-10-09

申请号：US15284070

申请日：2016-10-03

Applicant: STMicroelectronics International N.V.

Inventor： Danish Hasan Syed

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3181

Abstract: A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.

公开(公告)号：US10090845B1

公开(公告)日：2018-10-02

申请号：US15471483

申请日：2017-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Gagan Midha ,  Kallol Chatterjee

IPC: H03L7/08 ,  H03L7/06 ,  H03L7/093 ,  H03M3/00 ,  H03L7/081

Abstract: A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.

公开(公告)号：US10050606B2

公开(公告)日：2018-08-14

申请号：US15632202

申请日：2017-06-23

Applicant: STMicroelectronics International N.V.

Inventor： Neha Bhargava ,  Ankur Bal

IPC: H03H17/02 ,  H03H21/00

Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

公开(公告)号：US10044927B2

公开(公告)日：2018-08-07

申请号：US14886944

申请日：2015-10-19

Applicant: STMicroelectronics International N.V.

Inventor： Rosarium Pila

IPC: H04N5/232 ,  H04N1/21

Abstract: A method and apparatus for capturing stable images are disclosed. An ambient light sensor makes measurements of ambient light. A change in ambient light between two measurements is determined. If the change in ambient light measurements falls in a predefined range, then the change may be attributable to ambient light sensor being blocked by a user to trigger image capturing. Consequently, a camera is triggered to capture an image. Conversely, if the change in ambient light measurement is outside the range, image capturing is not triggered as the change may be attributable to other factors.

公开(公告)号：US10032506B2

公开(公告)日：2018-07-24

申请号：US15375987

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C7/22 ,  G11C7/06 ,  G11C11/419 ,  G11C11/418 ,  G06F1/06 ,  G06F13/16

CPC classification number: G11C11/419 ,  G06F1/06 ,  G06F13/1689 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

公开(公告)号：US10025726B2

公开(公告)日：2018-07-17

申请号：US14526686

申请日：2014-10-29

Applicant: STMicroelectronics International N.V.

Inventor： Herve Sibert ,  Loic Pallardy

IPC: G06F12/00 ,  G06F12/1036 ,  G06F12/1009

Abstract: A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry.

公开(公告)号：US09997236B1

公开(公告)日：2018-06-12

申请号：US15375390

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/418

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.

公开(公告)号：US09968700B2

公开(公告)日：2018-05-15

申请号：US14975200

申请日：2015-12-18

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Simon Dodd ,  Joseph Edward Scheffelin ,  Dave S. Hunt ,  Timothy James Hoekstra ,  Faiz Sherman ,  Stephan Gary Bush

IPC: A61L9/03 ,  B05B17/06 ,  A61L2/00 ,  A61L9/00

CPC classification number: A61L9/03 ,  A61L2/00 ,  A61L9/00 ,  B05B17/0684

Abstract: One or more embodiments are directed to a microfluidic delivery system that dispenses a fluid. The microfluidic delivery system may be provided in a variety of orientations. In one embodiment, the microfluidic delivery system is vertical so that fluid being expelled opposes gravity. In another embodiment, the microfluidic delivery system is orientated sideways so that fluid being expelled has a horizontal component. In yet another embodiment, the microfluidic delivery system faces downward.