公开(公告)号：US11714559B2

公开(公告)日：2023-08-01

申请号：US17033170

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Khaled Hamidouche ,  Hari S. Thangirala ,  Brandon Keith Potter

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0802

CPC classification number: G06F3/0619 ,  G06F3/067 ,  G06F3/0656 ,  G06F12/0223 ,  G06F12/0802 ,  G06F2212/152

Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.

公开(公告)号：US11709711B2

公开(公告)日：2023-07-25

申请号：US17120215

申请日：2020-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Guhan Krishnan

IPC: G06F9/46 ,  G06F9/50 ,  G06T1/60 ,  G06F13/16

CPC classification number: G06F9/5016 ,  G06F9/5022 ,  G06F13/1668 ,  G06T1/60

Abstract: An electronic device includes a memory; a plurality of clients; at least one arbiter circuit; and a management circuit. A given client of the plurality of clients communicates a request to the management circuit requesting an allocation of memory access bandwidth for accesses of the memory by the given client. The management circuit then determines, based on the request, a set of memory access bandwidths including a respective memory access bandwidth for each of the given client and other clients of the plurality of clients that are allocated memory access bandwidth. The management circuit next configures the at least one arbiter circuit to use respective memory access bandwidths from the set of memory access bandwidths for the given client and the other clients for subsequent accesses of the memory.

公开(公告)号：US11709670B2

公开(公告)日：2023-07-25

申请号：US16848681

申请日：2020-04-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Srinivasan Subramanian ,  Pruthvi K. Madugundu ,  Freddy Paul ,  Jagadish Krishnamoorthy ,  Diwakar Das ,  Praveen K. Jain

IPC: G06F9/50 ,  G06F9/54 ,  G06F9/445 ,  G06F9/455 ,  G06F8/71 ,  G06F16/14 ,  G06F16/176

CPC classification number: G06F8/71 ,  G06F9/445 ,  G06F16/148 ,  G06F16/176

Abstract: An electronic device includes a processor and a storage device having a file system with a plurality of directories. The processor executes an application that has a dependency on a shared library, the shared library having a dependency on a runtime component. When executing the application, the processor loads the shared library, the loading including executing a constructor for the shared library. Executing the constructor causes the processor to identify a selected directory where a compatible version of the runtime component is to be found based on a location of the shared library in the file system, the location of the shared library being determined from an application context from the application. When subsequently loading the runtime component for execution, the processor locates the runtime component in the selected directory.

公开(公告)号：US20230229603A1

公开(公告)日：2023-07-20

申请号：US17565666

申请日：2021-12-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： PHILIP NG ,  NIPPON RAVAL ,  DAVID A. KAPLAN ,  DONALD P. MATTHEWS, JR.

IPC: G06F13/10 ,  G06F12/084 ,  G06F12/1081

CPC classification number: G06F13/102 ,  G06F12/084 ,  G06F12/1081 ,  G06F2212/603

Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.

公开(公告)号：US20230222079A1

公开(公告)日：2023-07-13

申请号：US18185252

申请日：2023-03-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert E. Radke ,  Christopher M. Jaggers

IPC: G06F13/40 ,  H04B10/80

CPC classification number: G06F13/4027 ,  H04B10/801

Abstract: A system and method for efficient data transfer in a computing system are described. A computing system includes multiple nodes that receive tasks to process. A bridge interconnect transfers data between two processing nodes without the aid of a system bus on the motherboard. One of the multiple bridge interconnects of the computing system is an optical bridge interconnect that transmits optical information across the optical bridge interconnect between two nodes. The receiving node uses photonic integrated circuits to translate the optical information into electrical information for processing by electrical integrated circuits. One or more nodes switch between using an optical bridge interconnect and a non-optical bridge interconnect based on one or more factors such as measured power consumption and measured data transmission error rates.

公开(公告)号：US20230214232A1

公开(公告)日：2023-07-06

申请号：US17565593

申请日：2021-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： William Herz

IPC: G06F9/445 ,  G06F1/3206

CPC classification number: G06F9/4451 ,  G06F1/3206

Abstract: A processing device is provided which comprises memory and a processor, in communication with the memory. The processor is configured to acquire information indicating a sensory perception of a user, determine settings for one or more parameters used to control operation of the device based on the information indicating the sensory perception of the user and control the operation of the device by tuning the one or more parameters according to the determined settings.

公开(公告)号：US11693813B2

公开(公告)日：2023-07-04

申请号：US16427020

申请日：2019-05-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F13/1689 ,  G06F2213/0026

Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

公开(公告)号：US11693725B2

公开(公告)日：2023-07-04

申请号：US17536817

申请日：2021-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Johnathan Alsop ,  Shaizeen Aga

IPC: G06F11/07 ,  G06F11/24 ,  G06F11/14

CPC classification number: G06F11/0772 ,  G06F11/141 ,  G06F11/1471 ,  G06F11/24

Abstract: Detecting execution hazards in offloaded operations is disclosed. A second offload operation is compared to a first offload operation that precedes the second offload operation. It is determined whether the second offload operation creates an execution hazard on an offload target device based on the comparison of the second offload operation to the first offload operation. If the execution hazard is detected, an error handling operation may be performed. In some examples, the offload operations are processing-in-memory operations.

公开(公告)号：US20230209210A1

公开(公告)日：2023-06-29

申请号：US17564089

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Po-Min Wang ,  MuFan Yen

IPC: H04N5/235 ,  G06T7/00 ,  H04N5/247

CPC classification number: H04N5/2357 ,  G06T7/0002 ,  H04N5/247 ,  H04N5/2353 ,  G06T2207/10144 ,  G06T2207/20224 ,  G06T2207/30168

Abstract: A system for automatic image band detection includes concurrently capturing a first image of a scene with a first camera having a first exposure time and a second image of the scene with a second camera having a second exposure time. The system detects image banding for one of the first camera and the second camera based on the first image and the second image.

公开(公告)号：US20230208424A1

公开(公告)日：2023-06-29

申请号：US17563980

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Nur Mohammad Baksh ,  Deepesh John

IPC: H03K19/096 ,  H03K19/0185 ,  H03K3/012

CPC classification number: H03K19/0963 ,  H03K19/018521 ,  H03K3/012

Abstract: Systems, apparatuses, and methods for implementing a low-power single-phase logic gate latch for clock-gating are disclosed. A latch circuit includes shared clocked transistors without including clock inverters. The shared clocked transistors include a P-type clocked transistor and an N-type clocked transistor, with the clock input coupled to the gate of the P-type clocked transistor and to the gate of the N-type clocked transistor. The P-type clocked transistor is coupled between first and second transistor stacks of the latch. The N-type clocked transistor is coupled to a source gate of a first stack N-type transistor gated by a data input and to a source gate of a second stack N-type transistor gated by the inverted data input. The latch has a lower clock pin capacitance than a traditional logic gate latch while also avoiding having clock inverters which reduces dynamic power consumption.