公开(公告)号：US20170025996A1

公开(公告)日：2017-01-26

申请号：US14807538

申请日：2015-07-23

Applicant: ANALOG DEVICES GLOBAL

Inventor： GORDON CHEUNG ,  JOHN A. HAYDEN ,  HANS BRUEGGEMANN ,  AHMED ALI MOHAMED

IPC: H02S50/10 ,  G01R31/40 ,  G01R31/02

CPC classification number: H02S50/10 ,  G01R19/2509 ,  G01R31/025 ,  G01R31/40 ,  H02H1/0015 ,  H02H1/0092

Abstract: Switching interference is a primary artifact which affects the accuracy of arc detectors. To address switching interference, conventional arc detectors employ computationally intensive techniques which are often designed specifically for a target application. Thus, conventional arc detectors require a significant amount of hardware to accurately detect arc faults, which can increase costs of the power systems and prohibit wide deployment of arc detectors. With improved signal processing, a unique method for arc detection can accurately detect arc faults efficiently while tolerate switching interference from an inverter of the power system. Specifically, the method provides accurate but efficient arc detection by using a small Fast Fourier Transform with coherent sampling that is accomplished with a common clock generator in combination with signal conditioning. The overall system implementing the method is also programmable to suit a variety of target applications.

Abstract translation: 开关干扰是影响电弧检测器精度的主要工件。 为了解决切换干扰，常规电弧检测器采用通常专为目标应用设计的计算密集型技术。 因此，常规的电弧检测器需要大量的硬件来精确地检测电弧故障，这可以增加电力系统的成本并且禁止电弧检测器的广泛部署。 通过改进的信号处理，电弧检测的独特方法可以有效地准确检测电弧故障，同时容忍来自电力系统的逆变器的开关干扰。 具体地，该方法通过使用具有相干采样的小型快速傅立叶变换来提供精确而有效的电弧检测，其通过公共时钟发生器与信号调节相结合来完成。 实施该方法的整个系统也是可编程的，以适应各种目标应用。

公开(公告)号：US09553717B2

公开(公告)日：2017-01-24

申请号：US14218697

申请日：2014-03-18

Applicant: ANALOG DEVICES GLOBAL

Inventor： Muhammad Kalimuddin Khan ,  Philip Quinlan ,  Kenneth J. Mulvaney

IPC: H04L7/033 ,  H04L7/10 ,  H03L7/07 ,  H03L7/08 ,  H04L7/00

CPC classification number: H04L7/0331 ,  H03L7/07 ,  H03L7/0807 ,  H04L7/0016 ,  H04L7/046 ,  H04L7/10

Abstract: Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.

Abstract translation: 公开了用于时钟和数据恢复的装置和方法。 复位电路对输入信号的边沿之间的时钟周期进行计数，并且当时钟周期计数超出范围时，复位执行数据流的采集和跟踪的信号处理电路。 信号处理电路还被配置为根据校正的数据速率执行采集和跟踪，该数据速率可以通过相位误差校正控制环路的数据速率调整和/或两个数据速率之间的抖动来产生。

公开(公告)号：US20160380606A1

公开(公告)日：2016-12-29

申请号：US14754241

申请日：2015-06-29

Applicant: Analog Devices Global

Inventor： Aldrick S. Limjoco ,  Michael Cusack ,  Donal G. O'Sullivan ,  Patrick John Meehan ,  Thomas Conway

IPC: H03H7/01 ,  H01L23/31 ,  H01L23/552 ,  H01L25/16 ,  H05K1/11 ,  H05K3/30 ,  H05K3/28 ,  H05K1/18 ,  H05K1/02 ,  H05K7/06 ,  H01L23/495

CPC classification number: H05K1/111 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/552 ,  H01L25/16 ,  H01L2224/48247 ,  H01L2924/19105 ,  H05K1/0218 ,  H05K1/181 ,  H05K3/284 ,  H05K3/303 ,  H05K2201/1003 ,  H05K2201/1006

Abstract: An integrated electronic component assembly can include an electrically-conductive structure comprising two or more electrically-conductive terminals accessible on an exterior of the integrated electronic component assembly, a first component attachment region for a first component within the integrated electronic component assembly, and a second component attachment region for a second component within the integrated electronic component assembly. The integrated electronic component assembly can include an electrically-conductive magnetically-permeable shield coupled to or defined by the electrically-conductive structure, the electrically-conductive magnetically-permeable shield located between the first and second component attachment regions, including a portion extending in a direction out of a plane defined by the first and second component attachment regions, to suppress magnetic coupling between the first and second components.

Abstract translation: 集成电子部件组件可以包括导电结构，其包括可在集成电子部件组件的外部上接近的两个或更多个导电端子，用于集成电子部件组件内的第一部件的第一部件附接区域和第二部件附接区域 用于集成电子部件组件内的第二部件的部件附接区域。 集成电子部件组件可以包括耦合到导电结构或由导电结构限定的导电导磁屏蔽件，位于第一和第二部件附接区域之间的导电导磁屏蔽件，包括在 方向离开由第一和第二部件附接区域限定的平面，以抑制第一和第二部件之间的磁耦合。

公开(公告)号：US09513647B2

公开(公告)日：2016-12-06

申请号：US14673137

申请日：2015-03-30

Applicant: Analog Devices Global

Inventor： Ulrik Sørensen Wismar ,  Khiem Quang Nguyen

IPC: H03K17/04 ,  G05F1/575

CPC classification number: G05F1/575

Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.

Abstract translation: 本发明在一个方面涉及一种用于基于直流输入电压产生稳定的直流输出电压的直流线性稳压器电路。 DC线性稳压器电路包括DMOS传输晶体管，其包括漏极，栅极，源极和体积端子，其中漏极端子连接到调节器输出，该稳压器输出被配置为提供稳压的DC输出电压，并且源极端子连接到调节器输入 用于接收直流输入电压。 直流线性稳压器电路包括可切换的防漏电路，连接到DMOS传输晶体管的批量端子，并被配置为自动检测和中断从稳压器输出到散装端子的泄漏电流。

公开(公告)号：US20160349326A1

公开(公告)日：2016-12-01

申请号：US14721152

申请日：2015-05-26

Applicant: ANALOG DEVICES GLOBAL

Inventor： Richard F. Grafton ,  Chad R. Wentworth ,  Yashwanth Nagaraja

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31705

Abstract: A system, such as a system-on-chip, has a non-debug domain and a debug domain. The debug domain has a debug framework that enables a debugger driven, non-debug domain system reset. The system includes a reset control unit, and a debug trigger mechanism that includes a debug trigger interface (DTI) connected to the reset control unit. The DTI is configured to trigger the reset control unit to reset the non-debug domain. The DTI may further be configured to monitor a status of the non-debug domain system reset.

Abstract translation: 诸如片上系统的系统具有非调试域和调试域。 调试域具有调试框架，可以调试器驱动，非调试域系统重置。 该系统包括复位控制单元和调试触发机制，其包括连接到复位控制单元的调试触发接口（DTI）。 DTI配置为触发复位控制单元以重置非调试域。 还可以将DTI配置为监视非调试域系统重置的状态。

公开(公告)号：US20160329949A1

公开(公告)日：2016-11-10

申请号：US14919590

申请日：2015-10-21

Applicant: ANALOG DEVICES GLOBAL

Inventor： Mark Cloutier ,  Dragoslav Culum

IPC: H04B7/08

CPC classification number: H04B7/0885

Abstract: Apparatus and methods for scalable receivers are provided herein. In certain implementations, a scalable receiver system includes at least one analog-to-digital converter (ADC) that receives coded analog outputs from two or more receiver front ends. The receiver front ends system can process and code analog signals received from antennas using track and hold circuitry and various other circuitry such as filters and mixers.

Abstract translation: 本文提供了可伸缩接收机的装置和方法。 在某些实现中，可伸缩的接收机系统包括从两个或更多个接收器前端接收编码的模拟输出的至少一个模拟 - 数字转换器（ADC）。 接收机前端系统可以使用跟踪和保持电路以及各种其他电路（如滤波器和混频器）来处理和编码从天线接收的模拟信号。

公开(公告)号：US09448579B2

公开(公告)日：2016-09-20

申请号：US14136774

申请日：2013-12-20

Applicant: Analog Devices Global

Inventor： Stefan Marinca

IPC: G05F3/18

CPC classification number: G05F3/185

Abstract: Circuits and method for providing voltage reference circuits that include low drift over time and lower operating voltages are provided. Generally, it is desirable that a reference circuit provide an accurate and precise reference over time. The voltage reference circuits described can provide for good long term stability, operation at lower voltages than prior designs, consistent output voltage with reduced variability due to process changes and mismatches, low noise in the reference voltage, and other advantages.

Abstract translation: 提供用于提供包括随时间的低漂移和较低工作电压的电压参考电路的电路和方法。 通常，期望参考电路随时间提供精确和精确的参考。 所描述的电压参考电路可以提供良好的长期稳定性，在比以前的设计更低的电压下操作，一致的输出电压由于过程变化和不匹配而降低的可变性，参考电压中的低噪声以及其它优点。

公开(公告)号：US09444487B1

公开(公告)日：2016-09-13

申请号：US14838097

申请日：2015-08-27

Applicant: ANALOG DEVICES GLOBAL

Inventor： Dennis A. Dempsey

IPC: H03M1/38 ,  H03M1/78 ,  H03M1/68

CPC classification number: H03M1/785 ,  H03M1/682 ,  H03M1/765

Abstract: In an example, there is disclosed a multi-stage Digital to Analog Convertor, including: a first stage having a first set of circuit components, a second stage having a second set of circuit components and a third stage having a third set of circuit components, the third stage providing a load within first and second individual switchable impedance paths; wherein the DAC is operable in each of a first mode, a second mode and a third mode of operation, wherein in a first mode the first stage is switchably coupled to the second stage independently of the third stage; in a second mode, the load is coupled and presented to a first part of the second stage of circuit components and in a third mode the load is coupled and presented to a second, different, part of the second stage of circuit components. A corresponding system and method is also disclosed.

Abstract translation: 在一个示例中，公开了一种多级数模转换器，包括：第一级具有第一组电路部件，第二级具有第二组电路部件，第三级具有第三组电路部件 第三级在第一和第二可转换的阻抗路径内提供负载; 其中所述DAC可在第一模式，第二模式和第三操作模式中的每一个中操作，其中在第一模式中，所述第一级可独立于所述第三级可切换地耦合到所述第二级; 在第二模式中，负载被耦合并呈现给电路部件的第二级的第一部分，并且在第三模式中，负载耦合并呈现给第二级电路部件的第二，不同部分。 还公开了相应的系统和方法。

公开(公告)号：US09444444B2

公开(公告)日：2016-09-13

申请号：US13958141

申请日：2013-08-02

Applicant: Analog Devices Global

Inventor： Takashi Fujita

IPC: H03K17/16 ,  H03K17/042

CPC classification number: H03K17/165 ,  H03K17/04206 ,  H03K17/163 ,  H03K17/166

Abstract: A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.

Abstract translation: 驱动器可以在两个阶段中在开状态和断开状态之间提供开关的转换。 在第一阶段中，可以控制开关输出端的电压的电压转换速率。 在第二阶段，可以控制开关的电流梯度。 可以基于开关的输出端子处的电压值来进行第一级和第二级之间的转换。

公开(公告)号：US20160248319A1

公开(公告)日：2016-08-25

申请号：US14631429

申请日：2015-02-25

Applicant: Analog Devices Global

Inventor： Patrick J. Meehan ,  Thomas Conway ,  Adrian Paul Brokaw ,  Donal G. O'Sullivan

IPC: H02M1/44 ,  H03H7/01 ,  H02M3/158

CPC classification number: H02M1/44 ,  H02M1/15 ,  H02M3/158 ,  H03H7/0153 ,  H03H2007/013 ,  H03H2210/036

Abstract: A circuit and method to filter a signal is provided. The circuit includes a notch filter circuit to receive an input signal and first and second tuning signals and to provide an output signal. The notch filter circuit has an input-output frequency response that includes a stopband region. The stopband region has a center frequency and has an attenuation level that is based at least on a tuning signal. The tunable filter circuit further includes a tuning circuit operable in at least two modes to generate the tuning signal. The at least two modes includes a tuning mode and a filtering mode. The tuning circuit generates the tuning signal such that the attenuation level of the stopband region is greater in the filtering mode than in the tuning mode.

Abstract translation: 提供了一种滤波信号的电路和方法。 电路包括陷波滤波器电路，用于接收输入信号和第一和第二调谐信号并提供输出信号。 陷波滤波器电路具有包括阻带区域的输入 - 输出频率响应。 阻带区域具有中心频率并且具有至少基于调谐信号的衰减电平。 可调滤波器电路还包括可以以至少两种模式操作以产生调谐信号的调谐电路。 该至少两种模式包括调谐模式和滤波模式。 调谐电路产生调谐信号，使滤波模式下的阻带区域的衰减电平大于调谐模式。