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公开(公告)号：US20240095057A1
公开(公告)日：2024-03-21
申请号：US18457229
申请日：2023-08-28
Applicant: STMicroelectronics S.r.I.
Inventor： Giampiero Borgonovo , Lorenzo Re Fiorentin
IPC: G06F9/455
CPC classification number: G06F9/45558 , G06F2009/45583 , G06F2009/45595
Abstract: A system, for use in providing media access control (MAC)/router/switch/gateway features in an on-board communication network in a vehicle, includes MAC controllers configured to provide a MAC port layer controlling exchange of information over a data link, virtual machine (VM) bridge blocks configured to provide a MAC frame layer interfacing with System-on-Chip VMs, a software (SW) Ethernet port configured to receive from a host programming/configuration information for the system, a local memory controller configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (LMEM), and queue handlers configured to provide queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port, during cooperation with the LMEM via the local memory controller.
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公开(公告)号：US20230376229A1
公开(公告)日：2023-11-23
申请号：US17663847
申请日：2022-05-18
Applicant: STMicroelectronics S.r.I.
Inventor： Walter Girardi
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0602 , G06F3/0671
Abstract: A circuit for reading or writing a RAM includes a shift register coupled to the RAM, a test data input, and a test data output. The circuit further includes a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.
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公开(公告)号：US20230360716A1
公开(公告)日：2023-11-09
申请号：US18349565
申请日：2023-07-10
Applicant: STMicroelectronics S.r.I.
Inventor： Giampiero Borgonovo , Lorenzo Re Fiorentin
CPC classification number: G11C29/42 , G11C29/12015 , G11C29/18 , G11C29/4401
Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.
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254.发明公开公开(公告)号：US20230350840A1
公开(公告)日：2023-11-02
申请号：US17732114
申请日：2022-04-28
Applicant: STMicroelectronics S.r.I.
Inventor： Daniele Oreggia , Alessandro Cannone , Diego Alagna , Marcello Raimondi
IPC: G06F13/42 , G06F13/364 , G06F13/40
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/4022
Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.
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公开(公告)号：US20230232165A1
公开(公告)日：2023-07-20
申请号：US18151207
申请日：2023-01-06
Applicant: STMicroelectronics S.R.I.
Inventor： Paolo Angelini , Roberto Pio Baorda
IPC: H04R19/04 , G01R19/165
CPC classification number: H04R19/04 , G01R19/16576 , H04R2201/003
Abstract: A read circuit for capacitive sensors such as a MEMS microphones includes a sensor node configured to be coupled to a capacitive sensor to apply a bias voltage to the sensor and sense the capacitance value of the sensor wherein the voltage at the sensor node is indicative of the capacitance value of the capacitive sensor. A switch is provided between the sensor node and the intermediate node. A shock detector coupled to the sensor node and the switch asserts a shock signal to make the switch conductive in response to a shock applied to the capacitive sensor, and de-asserts the shock signal to make the switch non-conductive with a delay after the end of the shock applied to the capacitive sensor.
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Patent Agency Ranking
公开(公告)号：US20230143391A1
公开(公告)日：2023-05-11
申请号：US17523561
申请日：2021-11-10
Applicant: STMicroelectronics S.r.I.
Inventor： Claudio Adragna
CPC classification number: H02M3/33592 , H02M1/08
Abstract: In an embodiment, a method for controlling a synchronous rectifier (SR) transistor of a flyback converter includes: determining a first voltage across conduction terminals of the SR transistor; asserting a turn-on signal when a body diode of the SR transistor is conducting current; asserting a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generating a gating signal based on an output voltage of the flyback converter and on the first voltage; turning on the SR transistor based on the turn-on signal and on the gating signal; and turning off the SR transistor based on the turn-off signal.
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公开(公告)号：US20230137601A1
公开(公告)日：2023-05-04
申请号：US18046818
申请日：2022-10-14
Applicant: STMicroelectronics S.r.I.
Inventor： Enrico Rosario Alessi , Fabio Passaniti
Abstract: In an embodiment a method for detecting an activity of a first eye of a user using glasses includes acquiring, by a controller and through first and second electrodes, a first electrostatic charge variation signal indicative of a difference between the electrostatic charge variations detected by the first and the second electrodes, verifying, by the controller, a presence of one or more blink patterns in the first electrostatic charge variation signal, each blink pattern being indicative of a respective click or of a respective blink, the click being a voluntary blink of the first eye and the blink being an involuntary blink of the first eye, when the first electrostatic charge variation signal has the one or more blink patterns, determining, by the controller for each blink pattern, whether a first condition is verified, when the first condition is not verified, detecting, by the controller, a respective blink and when the first condition is verified, detecting, by the controller, a respective click.
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公开(公告)号：US20230118016A1
公开(公告)日：2023-04-20
申请号：US18064631
申请日：2022-12-12
Applicant: STMicroelectronics S.r.I.
Inventor： Francesco Pirozzi , Santi Carlo Adamo
Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.
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公开(公告)号：US20230087074A1
公开(公告)日：2023-03-23
申请号：US17940753
申请日：2022-09-08
Applicant: STMicroelectronics S.r.I.
Inventor： Gianbattista Lo Giudice , Antonino Conte
Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.
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260.发明申请公开(公告)号：US20220263541A1
公开(公告)日：2022-08-18
申请号：US17662127
申请日：2022-05-05
Applicant: STMicroelectronics S.r.I.
Inventor： Matteo Varesio , Paolo Treffiletti
Abstract: A communication network comprises a plurality of electronic devices coupled via a plurality of communication links. The communication links comprise links over a first physical medium and links over a second physical medium. A method of operating the network comprises issuing, at an originator device, a path request message directed towards a destination device, transmitting the path request message from the originator device to the destination device through a first set of intermediate devices via a forward sequence of links, issuing, at the destination device, a path reply message directed towards the originator device, and transmitting the path reply message from the destination device to the originator device through a second set of intermediate devices via a reverse sequence of links.
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