公开(公告)号：US20150162194A1

公开(公告)日：2015-06-11

申请号：US14102873

申请日：2013-12-11

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Yiheng Xu ,  John Zhang

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/0337 ,  B81C1/0046 ,  G03F7/0002 ,  H01L21/31144

Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.

Abstract translation: 本发明的实施例提供一种形成装置图案的方法。 该方法包括定义要在设备层中创建的设备模式; 在器件层的顶部上形成牺牲层; 识别在其高度的位置处具有表示装置图案的水平横截面形状的压印模具; 将压印模均匀地推入牺牲层，直到至少压印模具的位置达到被压印模推送的牺牲层内的水平面; 将所述压印模具远离所述牺牲层移除; 在由牺牲层中的压印模制成的凹部中形成硬掩模，硬掩模具有表示装置图案的图案; 并将硬掩模的图案转移到器件层的下方。

公开(公告)号：US20150140760A1

公开(公告)日：2015-05-21

申请号：US14597457

申请日：2015-01-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Pierre Morin

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract translation: 描述形成应变通道鳍状FET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 可以将第一薄外延层切割并用于通过弹性弛豫向finFET的相邻沟道区施加应变。 该结构表现出优选的设计范围，用于增加应变在翅片高度上的诱导应变和均匀性。

公开(公告)号：US09032354B2

公开(公告)日：2015-05-12

申请号：US13903847

申请日：2013-05-28

Applicant: STMicroelectronics, Inc.

Inventor： Razak Hossain

IPC: G06F17/50 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318575 ,  G01R31/318577

Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

公开(公告)号：US20150126003A1

公开(公告)日：2015-05-07

申请号：US14596625

申请日：2015-01-14

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu

IPC: H01L21/8238 ,  H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823821 ,  H01L21/845

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made on the bottom portion to produce a silicon-germanium region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由硅半导体材料形成的SOI衬底层包括相邻的第一和第二区域。 去除第二区域中的硅衬底层的一部分，使得第二区域保持由硅半导体材料制成的底部。 硅 - 锗半导体材料的外延生长在底部制成以产生硅 - 锗区。 图案化硅区域以限定第一（例如，n沟道）导电类型的FinFET的第一鳍结构。 硅 - 锗区域也被图案化以限定第二（例如p沟道）导电类型的FinFET的第二鳍结构。

公开(公告)号：US20150118805A1

公开(公告)日：2015-04-30

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L21/265 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US20150116090A1

公开(公告)日：2015-04-30

申请号：US14508008

申请日：2014-10-07

Applicant: STMicroelectronics, Inc.

Inventor： Gregory Proehl

IPC: H04B5/00 ,  G06K7/10 ,  H01F38/14

CPC classification number: H04B5/0037 ,  G06K7/10297 ,  H01F27/362 ,  H01F38/14 ,  H04B5/0031 ,  H04B5/0075

Abstract: A near-field magnetic induction system includes a metallic structure, an amorphous metal barrier and a near-field magnetic induction device. The device includes an antenna coupled to the amorphous metal barrier and a circuit electrically coupled to the antenna. In use, the antenna is separated from the metallic structure by the amorphous metal barrier. The amorphous metal barrier may be integrated with the near-field magnetic induction device or with the metallic structure. Inductive coupling with the near-field magnetic induction device may be used, for example, in communication or energy transfer applications such as RFID tags and inductive chargers.

Abstract translation: 近场磁感应系统包括金属结构，非晶金属屏障和近场磁感应装置。 该装置包括耦合到非晶金属屏障的天线和电耦合到天线的电路。 在使用中，天线通过非晶金属屏障与金属结构分离。 非晶态金属屏障可以与近场磁感应装置或金属结构集成。 与近场磁感应装置的感应耦合可用于例如通信或能量转移应用，如RFID标签和感应充电器。

公开(公告)号：US09018051B2

公开(公告)日：2015-04-28

申请号：US14164055

申请日：2014-01-24

Applicant: STMicroelectronics, Inc.

Inventor： Barry Dove

IPC: H01L21/335 ,  H01L29/66 ,  H01L21/28 ,  H01L23/522 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L21/28114 ,  H01L23/5226 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.

Abstract translation: 提供了一种应变增强型晶体管，其具有覆盖栅电极的应变诱导层。 栅电极在晶体管的沟道区域上具有倾斜的侧壁。

公开(公告)号：US20150108585A1

公开(公告)日：2015-04-23

申请号：US14587872

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Prasanna KHARE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/16

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel and the substrate. Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate. The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions.

Abstract translation: 可以通过在半导体沟道和衬底之间插入绝缘层来防止FinFET器件中的沟道对衬底的泄漏。 类似地，通过在源极/漏极区域和衬底之间插入绝缘层，可以防止FinFET器件中的源极/漏极到衬底的泄漏。 绝缘层在物理和电气上隔离了基板的导电路径，从而防止电流泄漏。 如果半导体翅片的阵列由多层堆叠构成，则可以去除底部材料，从而产生悬浮在硅表面上方的翅片阵列。 然后可以用氧化物填充剩下的顶部翅片材料之下的产生的间隙，以更好地支撑翅片并将翅片阵列与基底隔离开。 所得到的FinFET器件在栅极区域和源极/漏极区域中完全衬底隔离。

公开(公告)号：US20150102496A1

公开(公告)日：2015-04-16

申请号：US14053531

申请日：2013-10-14

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal interconnections are formed in an integrated circuit by forming a wide trench in a dielectric layer. A dielectric fin of a second dielectric material is formed in the trench. Conductive plugs and metal lines are formed on both sides of the fin.

Abstract translation: 通过在电介质层中形成宽的沟槽，在集成电路中形成金属互连。 在沟槽中形成第二电介质材料的绝缘片。 导电插头和金属线形成在鳍的两侧。

公开(公告)号：US20150102412A1

公开(公告)日：2015-04-16

申请号：US14050576

申请日：2013-10-10

Applicant: STMicroelectronics, Inc.

Inventor： PIERRE MORIN ,  Qing Liu ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上半导体（SOI）晶片的第一半导体层上形成第二半导体层，该第二半导体层包括与第一半导体层的第一半导体材料不同的第二半导体材料。 该方法还可以包括在非氧化性气氛中进行热处理，以将第二半导体材料扩散到第一半导体层中，以及去除第二半导体层。