公开(公告)号：US10249535B2

公开(公告)日：2019-04-02

申请号：US15433188

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Chanemougame ,  Lars Liebmann ,  Nigel Cave

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/78

Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.

公开(公告)号：US10248754B2

公开(公告)日：2019-04-02

申请号：US15602810

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Fadi Batarseh ,  Karthik Krishnamoorthy ,  Ahmed Omran

IPC: G06F17/50

Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.

公开(公告)号：US20190096677A1

公开(公告)日：2019-03-28

申请号：US15712301

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417

Abstract: One illustrative method disclosed includes selectively forming sacrificial conductive source/drain cap structures on and in contact with first and second source/drain contact structures positioned on opposite sides of a gate of a transistor and removing and replacing the spaced-apart sacrificial conductive source/drain cap structures with first and second separate, laterally spaced-apart insulating source/drain cap structures that are positioned on the first and second source/drain contact structures. The method also includes forming a gate contact opening that extends through a space between the insulating source/drain cap structures and through the gate cap so as to expose a portion of the gate structure and forming a conductive gate contact structure (CB) that is conductively coupled to the gate structure.

公开(公告)号：US10243074B2

公开(公告)日：2019-03-26

申请号：US15693938

申请日：2017-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/324 ,  H01L29/417

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

公开(公告)号：US10243053B1

公开(公告)日：2019-03-26

申请号：US15876316

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Chanro Park

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/417 ,  H01L21/28 ,  H01L23/528 ,  H01L29/78

Abstract: One illustrative IC product disclosed herein includes a gate structure for a transistor, a conductive source/drain contact structure and an insulating source/drain cap structure positioned above the conductive source/drain contact structure, wherein the insulating source/drain cap structure has a first notch formed therein. In one illustrative example, the product also includes a sidewall spacer that has a second notch in an upper portion of the sidewall spacer, wherein a first portion of the insulating source/drain cap structure is positioned in the second notch, and a conductive gate contact structure comprising first and second portions, the first portion of the conductive gate contact structure being positioned in the first notch and the second portion of the conductive gate contact structure being in contact with the gate structure.

公开(公告)号：US20190088764A1

公开(公告)日：2019-03-21

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Steven BENTLEY ,  Puneet Harischandra SUVARNA ,  Chanro PARK ,  Min Gyu SUNG ,  Lars LIEBMANN ,  Su Chen FAN ,  Brent ANDERSON

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20190088478A1

公开(公告)日：2019-03-21

申请号：US15709730

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Garo J. Derderian ,  Jinping Liu

IPC: H01L21/033 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66

Abstract: The disclosure is directed to methods for forming a set of fins from a substrate. One embodiment of the disclosure includes: providing a stack over the substrate, the stack including a first oxide over the substrate, a first nitride over the pad oxide, a second oxide over the first nitride, and a first hardmask over the second oxide; patterning the first hard mask to form a first set of hardmask fins over the second oxide; oxidizing the first set of hardmask fins to convert the first set of hardmask fins into a set of oxide fins; using the set of oxide fins as a mask, etching the second oxide and the first nitride to expose portions of the first oxide thereunder such that remaining portions of the second oxide and the first nitride remain disposed beneath the set of oxide fins thereby defining a set of mask stacks; and using the set of mask stacks as a mask, etching the exposed portions of the first oxide and the substrate thereby forming the set of fins from the substrate.

公开(公告)号：US10236379B2

公开(公告)日：2019-03-19

申请号：US15593651

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Puneet Harischandra Suvarna ,  Julien Frougier ,  Bartlomiej Jan Pawlak

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.

公开(公告)号：US10236358B1

公开(公告)日：2019-03-19

申请号：US15784445

申请日：2017-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Jagar Singh

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02

Abstract: Structures for a field-effect transistor and methods for forming a field-effect transistor. The structure includes a gate structure having a sidewall and a sidewall spacer arranged adjacent to the sidewall of the gate structure. The sidewall spacer includes an energy removal film material and one or more air gaps in the energy removal film material.

公开(公告)号：US10236296B1

公开(公告)日：2019-03-19

申请号：US15861097

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Chanemougame ,  Emilie Bourjot ,  Bipul C. Paul

IPC: H01L27/11 ,  H01L29/78 ,  H01L23/528 ,  H01L23/535

Abstract: An IC product disclosed herein includes a first merged doped source/drain (MDSD) region having an upper surface, a first side surface and a second side surface that intersect one another at a corner of the first merged doped source/drain region, a second MDSD region and a contact trench in an isolation structure positioned between the first and second MDSD regions. The product also includes a conductive gate structure positioned above at least the second MDSD region and a cross-coupled contact structure that comprises a first portion positioned within the contact trench laterally adjacent to and conductively coupled to at least one of the first side surface and the second side surface, and a second portion that is positioned above and conductively coupled to the upper surface of the MDSD region, wherein the cross-coupled contact structure is conductively coupled to the conductive gate structure.