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261.发明授权公开(公告)号：US10393804B2
公开(公告)日：2019-08-27
申请号：US16170479
申请日：2018-10-25
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Nimit Endlay , Balwinder Singh Soni
IPC: G01R31/3177 , G01R31/3193 , G06F11/26 , G06F11/25 , G06F11/27 , G01R31/317 , G01R31/319
Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.
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公开(公告)号：US20190227096A1
公开(公告)日：2019-07-25
申请号：US16257694
申请日：2019-01-25
Inventor： Mahesh CHOWDHARY , Arun KUMAR , Ghanapriya SINGH , Rajendar BAHL
Abstract: A distributed computing system for artificial intelligence in autonomously appreciating a circumstance context of a smart device. Raw context data is detected by sensors associated with the smart device. The raw context data is pre-processed by the smart device and then provided to a cloud based server for further processing. At the cloud based server, various sets of feature data are obtained from the pre-processed context data. The various sets of feature data are compared with corresponding classification parameters to determine a classification of a continuous event and/or a classification of transient event, if any, which occur in the context. The determined classification of the continuous event and the transient event will be used to autonomously configure the smart device or another related smart device to fit the context.
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公开(公告)号：US10348314B2
公开(公告)日：2019-07-09
申请号：US15888153
申请日：2018-02-05
Applicant: STMicroelectronics International N.V.
Inventor： Anand Kumar , Gagan Midha
Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.
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264.发明申请公开(公告)号：US20190158858A1
公开(公告)日：2019-05-23
申请号：US16251798
申请日：2019-01-18
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Sumit Johar , Surinder Pal Singh
IPC: H04N19/433
Abstract: Video encoders and decoders and video encoding and decoding methods are provided. A video encoder includes an input buffer configured to receive a video data stream and to supply current frame data, a frame buffer configured to store reconstructed frame data, and an encoder circuit configured to read reference frame data from the frame buffer, to encode the current frame data received from the input buffer using the reference frame data and to write the reconstructed frame data to the frame buffer. The encoder circuit may be configured to write the reconstructed frame data by overwriting the reference frame data in the frame buffer.
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公开(公告)号：US10284201B1
公开(公告)日：2019-05-07
申请号：US15877970
申请日：2018-01-23
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Vikas Rana
IPC: H03L5/00 , H03K19/00 , H03K19/017 , H03K19/0185
Abstract: A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.
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Patent Agency Ranking
公开(公告)号：US20190129790A1
公开(公告)日：2019-05-02
申请号：US15798916
申请日：2017-10-31
Inventor： Om Ranjan , Riccardo Gemelli , Abhishek Gupta
CPC classification number: G06F11/10 , G06F3/0619 , G06F3/064 , G06F3/0673 , H04L1/0045 , H04L1/0063 , H04L1/0082
Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
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公开(公告)号：US20190128960A1
公开(公告)日：2019-05-02
申请号：US15797504
申请日：2017-10-30
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Tejinder KUMAR , Akshat JAIN
IPC: G01R31/317 , G01R31/3177
Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.
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公开(公告)号：US20190094296A1
公开(公告)日：2019-03-28
申请号：US15713168
申请日：2017-09-22
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Srinivas Dhulipalla
IPC: G01R31/28
CPC classification number: G01R31/2896 , G01R31/2856 , G01R31/2886 , H03K19/20
Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.
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公开(公告)号：US20190086474A1
公开(公告)日：2019-03-21
申请号：US15710172
申请日：2017-09-20
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Srinivas Dhulipalla
IPC: G01R31/327 , H03K19/20
Abstract: A method of operating an electronic device during test mode operation of a duplicated voltage monitor includes sensing a functional supply voltage with a voltage monitor, deasserting an output of the voltage monitor if the functional supply voltage is exceeds a threshold, and asserting output of the voltage monitor if the functional supply voltage falls below the threshold. A test supply voltage is sensed with the duplicate voltage monitor, output of the duplicate voltage monitor is deasserted if the test supply voltage exceeds a threshold, and output of the duplicate voltage monitor is asserted if the test supply voltage falls below the threshold. Output of the duplicate voltage monitor is monitored to thereby determine the threshold based upon assertion of the output of the duplicate voltage monitor, and performing a logical operation between outputs of the voltage monitor and the duplicate voltage monitor to generate a power on reset signal.
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270.发明授权公开(公告)号：US10228420B2
公开(公告)日：2019-03-12
申请号：US15268848
申请日：2016-09-19
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Nimit Endlay , Balwinder Singh Soni
IPC: G01R31/317 , G01R31/3177 , G01R31/3193 , G06F11/26 , G06F11/25 , G06F11/27
Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.
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