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    RAPID TAG INVALIDATION CIRCUIT
    261.
    发明公开
    RAPID TAG INVALIDATION CIRCUIT 审中-公开

    公开(公告)号：US20230206995A1

    公开(公告)日：2023-06-29

    申请号：US17564680

    申请日：2021-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Russell Schreiber ,  Kyle David Whittle

    IPC: G11C11/4099 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4096

    CPC classification number: G11C11/4099 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4096

    Abstract: A system and method for efficiently resetting data stored in a memory array are described. In various implementations, an integrated circuit includes a memory for storing data, and a processing unit that generates access requests for the data stored in the memory. When access circuitry of the memory array begins a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value less than a threshold voltage of transistors. Therefore, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuitry provides the reset data on the write bit lines, and asserts each of the write word lines of the memory array. To complete the write operation, the access circuitry returns the power supply voltage level from below the threshold voltage level to an operating voltage level.

    SYSTEMS AND METHOD FOR GENERATING MORTON CODE
    263.
    发明公开
    SYSTEMS AND METHOD FOR GENERATING MORTON CODE 审中-公开

    公开(公告)号：US20230206509A1

    公开(公告)日：2023-06-29

    申请号：US17562842

    申请日：2021-12-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Alexandre Tsakok

    IPC: G06T9/00 ,  G06T9/20

    CPC classification number: G06T9/001 ,  G06T9/20

    Abstract: Methods and systems are disclosed for encoding a Morton code. Techniques disclosed comprise receiving location vectors associated with primitives, where the primitives are graphical elements spatially located within a three-dimensional scene. Techniques further comprise determining a code pattern comprising a prefix pattern and a base pattern, and, then, coding each of the location vectors according to the code pattern.

    APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS AND NON-NEAR-MEMORY PROCESSING COMMANDS IN A MEMORY CONTROLLER
    264.
    发明公开
    APPROACH FOR MANAGING NEAR-MEMORY PROCESSING COMMANDS AND NON-NEAR-MEMORY PROCESSING COMMANDS IN A MEMORY CONTROLLER 审中-公开

    公开(公告)号：US20230205706A1

    公开(公告)日：2023-06-29

    申请号：US17561454

    申请日：2021-12-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Niti Madan ,  John Kalamatianos

    IPC: G06F12/1009 ,  G06F12/0882 ,  G06F12/02

    CPC classification number: G06F12/1009 ,  G06F12/0882 ,  G06F12/0207

    Abstract: An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria. The memory controller maintains and uses a page table to properly configure memory elements, such as banks in a memory module, for the next memory command, whether a PIM command or a non-PIM command. The page table tracks the status of memory elements as of the most recent memory command that was issued. The page table includes an “All Bank” entry that indicates the status of banks after processing the most recent PIM command. For example, the All Banks entry indicates whether all the banks have a row open and if so, specifies the open row for all the banks.

    LEVERAGING PROCESSING-IN-MEMORY (PIM) RESOURCES TO EXPEDITE NON-PIM INSTRUCTIONS EXECUTED ON A HOST
    265.
    发明公开
    LEVERAGING PROCESSING-IN-MEMORY (PIM) RESOURCES TO EXPEDITE NON-PIM INSTRUCTIONS EXECUTED ON A HOST 审中-公开

    公开(公告)号：US20230205693A1

    公开(公告)日：2023-06-29

    申请号：US17564155

    申请日：2021-12-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： JAGADISH B. KOTRA ,  JOHN KALAMATIANOS ,  YASUKO ECKERT ,  YONGHAE KIM

    IPC: G06F12/0811

    CPC classification number: G06F12/0811

    Abstract: Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host is disclosed. In an implementation, a memory controller identifies a first write instruction to write first data to a first memory location, where the first write instruction is not a processing-in-memory (PIM) instruction. The memory controller then writes the first data to a first PIM register. Opportunistically, the memory controller moves the first data from the first PIM register to the first memory location. In another implementation, a memory controller identifies a first memory location associated with a first read instruction, where the first read instruction is not a processing-in-memory (PIM) instruction. The memory controller identifies that a PIM register is associated with the first memory location. The memory controller then reads, in response to the first read instruction, first data from the PIM register.

    PRIORITY INVERSION MITIGATION
    266.
    发明公开
    PRIORITY INVERSION MITIGATION 审中-公开

    公开(公告)号：US20230205602A1

    公开(公告)日：2023-06-29

    申请号：US17564074

    申请日：2021-12-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Yash UKIDAVE ,  Randy Ramsey ,  Nishank Pathak ,  Baturay Turkmen

    IPC: G06F9/50 ,  G06T1/20

    CPC classification number: G06F9/5083 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/5016 ,  G06T1/20

    Abstract: Parallel processors typically allocate resources to workloads based on workload priority. Priority inversion of resource allocation between workloads of different priorities reduces the operating efficiency of a parallel processor in some cases. A parallel processor mitigates priority inversion by soft-locking resources to prevent their allocation for the processing of lower priority workloads. Soft-locking is enabled responsive to a soft-lock condition, such as one or more priority inversion heuristics exceeding corresponding thresholds or multiple failed allocations of higher priority workloads within a time period. In some cases, priority inversion heuristics include quantities of higher priority workloads and lower priority workloads that are in-flight or incoming, ratios between such quantities, quantities of render targets, or a combination of these. The soft-lock is released responsive to expiry of a soft-lock timer or incoming or in-flight higher priority workloads falling below a threshold, for example.

    LOAD AND STORE MATCHING BASED ON ADDRESS COMBINATION
    267.
    发明公开
    LOAD AND STORE MATCHING BASED ON ADDRESS COMBINATION 审中-公开

    公开(公告)号：US20230205525A1

    公开(公告)日：2023-06-29

    申请号：US17564173

    申请日：2021-12-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Sadayan Ghows Ghani Sadayan Ebramsah Mo Abdul

    IPC: G06F9/30

    CPC classification number: G06F9/30043

    Abstract: A processor identifies matches between a load operation and a plurality of more store operations based on an address vector that represents a combination of addresses targeted by the store operations. The address vector is used to identify a potential match between an address targeted by the load operation and at least one of the addresses targeted by the plurality of store operations. This allows the processor to quickly identify when there are no potential matches between the load operation and any of the plurality of store operations, thereby reducing overhead at the processor and improving overall processing efficiency.

    AUTOMATED USE OF COMPUTATIONAL MOTIFS VIA DEEP LEARNING DETECTION
    268.
    发明公开
    AUTOMATED USE OF COMPUTATIONAL MOTIFS VIA DEEP LEARNING DETECTION 审中-公开

    公开(公告)号：US20230205517A1

    公开(公告)日：2023-06-29

    申请号：US17562921

    申请日：2021-12-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jakub Kurzak ,  Nicholas Penha Malaya

    IPC: G06F8/71 ,  G06F8/41 ,  G06F9/455

    CPC classification number: G06F8/71 ,  G06F8/4434 ,  G06F8/4432 ,  G06F9/45516

    Abstract: A system and method are described for efficiently utilizing optimized implementations of computational patterns in an application. In various implementations, a computing system includes at least one or more processors, and these one or more processors and other hardware resources of the computing system process a variety of applications. Sampled, dynamic values of hardware performance counters are sent to a trained data model. The data model provides characterization of the computational patterns being used and the types of workloads being processed. The data model also indicates whether the identified computational patterns already use an optimized version. Later, a selected processor determines a given unoptimized computational pattern is no longer running and replaces this computational pattern with an optimized version. Although the application is still running, the processor performs a static replacement. On a next iteration of the computational pattern, the optimized version is run.

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