公开(公告)号：US20150271677A1

公开(公告)日：2015-09-24

申请号：US14633913

申请日：2015-02-27

Applicant: STMicroelectronics (Rousset) SAS ,  Proton World International N.V.

Inventor： Olivier Van Nieuwenhuyze ,  Christophe Henri Ricard

IPC: H04W12/08 ,  H04W4/00

CPC classification number: H04W12/08 ,  H04L63/0492 ,  H04W4/80 ,  H04W12/06 ,  H04W12/12

Abstract: A processing device of an NFC device receives a request, initiated by a first application loaded in a memory of the NFC device, to modify one or more parameters of an NFC routing table of an NFC router of the NFC device. The NFC routing table has parameters indicating the devices to which NFC messages are to be routed. The processing device retrieves a first identifier associated with the application and transmits the first identifier to the NFC router. The NFC router, based on the first identifier, verifies whether or not the application is authorized to modify the routing table.

Abstract translation: NFC设备的处理设备接收由加载在NFC设备的存储器中的第一应用启动的请求，以修改NFC设备的NFC路由器的NFC路由表的一个或多个参数。 NFC路由表具有指示NFC消息要路由到的设备的参数。 处理设备检索与应用相关联的第一标识符，并将第一标识符发送到NFC路由器。 NFC路由器基于第一标识符来验证应用是否被授权修改路由表。

公开(公告)号：US09142951B2

公开(公告)日：2015-09-22

申请号：US14041654

申请日：2013-09-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Antoine Pavlin

IPC: H02H3/18 ,  H01L27/02 ,  H01L27/088 ,  H02H11/00

CPC classification number: H02H3/18 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/088 ,  H02H11/003

Abstract: Disclosed herein is a device comprising a protection circuit configured to protect against a polarity reversal of the input DC power supply voltage, the protection circuit comprising an N-channel main transistor having a source coupled to an input terminal and having a drain coupled to an output terminal, a command circuit configured to render the main transistor blocked in the event of a polarity reversal and conducting otherwise, and a control circuit configured to dynamically adjust the bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor according to the value of the voltages present at the source and the drain of the main transistor and the type of conductivity of the substrate regions.

Abstract translation: 本文公开了一种包括保护电路的装置，其被配置为防止输入DC电源电压的极性反转，该保护电路包括N沟道主晶体管，其具有耦合到输入端子的源极，并且具有耦合到输出的漏极 端子，命令电路，其被配置为在极性反转的情况下使主晶体管阻塞并且否则导通;以及控制电路，被配置为通过将衬底区域连接来动态地调节连接到主晶体管的各个部件的衬底区域的偏置 根据存在于主晶体管的源极和漏极上的电压值以及衬底区域的导电类型，到主晶体管的源极或漏极。

公开(公告)号：US09121896B2

公开(公告)日：2015-09-01

申请号：US14082818

申请日：2013-11-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: G01R27/08 ,  G01R31/28 ,  G01L9/00 ,  G06K19/073 ,  H01L21/66 ,  H01L23/00

CPC classification number: G01R31/2851 ,  G01L9/0042 ,  G06K19/07363 ,  G06K19/07381 ,  H01L22/34 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.

Abstract translation: 一种用于检测集成电路芯片的基板的减薄的装置，包括在基板的有源区域中连接为惠斯通电桥的条形扩散电阻器，其中：桥的第一相对电阻器沿第一 方向; 桥的第二相对电阻器沿着第二方向定向; 并且第一和第二方向使得衬底的变薄导致桥的不平衡值的变化。

公开(公告)号：US09052345B2

公开(公告)日：2015-06-09

申请号：US13654991

申请日：2012-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Thierry Soude

IPC: G01R27/08 ,  H01L23/00

CPC classification number: G01R27/08 ,  G01R31/2856 ,  G01R31/311 ,  G01R31/31719 ,  G09C1/00 ,  H01L23/576 ,  H01L2924/0002 ,  H04L9/004 ,  H04L2209/12 ,  H01L2924/00

Abstract: A system for detecting a laser attack on an integrated circuit chip formed in a semiconductor substrate, including a detection device capable of detecting voltage variations of the substrate. The system includes P-type first wells and N-type second wells extending in a P-type upper portion of the substrate; an N-type buried layer extending under at least a portion of the first and second wells; biasing contacts for the second wells and the buried layer; ground contacts for the first wells; and substrate contacts for detecting a substrate voltage, the detection contacts surrounding the first and second wells. The detection device comprises a resistor having a first terminal connected to said ground contacts of the first wells and a second terminal connected to said substrate contacts; and a comparator connected in with the resistor configured to detect a potential difference across the resistor.

Abstract translation: 一种用于检测形成在半导体衬底中的集成电路芯片上的激光攻击的系统，包括能够检测衬底的电压变化的检测装置。 该系统包括在基板的P型上部中延伸的P型第一阱和N型第二阱; 在所述第一和第二孔的至少一部分下延伸的N型掩埋层; 用于第二井和埋层的偏压接触; 第一口井的地面接触; 以及用于检测衬底电压的衬底触点，围绕第一和第二阱的检测触点。 检测装置包括电阻器，其具有连接到第一阱的所述接地触点的第一端子和连接到所述衬底触点的第二端子; 以及与电阻器连接的比较器，被配置为检测电阻器两端的电位差。

公开(公告)号：US20150145564A1

公开(公告)日：2015-05-28

申请号：US14536122

申请日：2014-11-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard ,  Michel Cuenca

IPC: H03K17/16 ,  H03K17/687 ,  H03K3/012

CPC classification number: H03K17/161 ,  G11C27/024 ,  H03K3/012 ,  H03K17/6872

Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.

Abstract translation: 一种方法用于控制包括具有主MOS晶体管的开关单元的电子器件，所述主MOS晶体管具有衬底，第一导电电极和耦合到输出端子的第二导电电极。 该方法包括以这样的方式控制主晶体管，使其处于导通状态或截止状态，使得当主晶体管处于导通状态时，主晶体管的基板和第一导电电极连接到 输入端子，并且当主晶体管处于截止状态时，主晶体管的第一导电电极与输入端隔离，并且第一偏置电压被施加到第一导电电极，并且第二偏置电压施加到 主晶体管的衬底。

公开(公告)号：US20150145487A1

公开(公告)日：2015-05-28

申请号：US14612063

申请日：2015-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jimmy Fort ,  Thierry Soude

IPC: G05F1/46

CPC classification number: G05F3/267 ,  G05F1/468 ,  G05F3/30

Abstract: According to an embodiment, generating an adjustable bandgap reference voltage includes generating a current proportional to absolute temperature (PTAT). Generating the PTAT current includes equalizing voltages across the terminals of a core that is designed to be traversed by the PTAT current. Generating the adjustable bandgap reference also includes generating a current inversely proportional to absolute temperature (CTAT), summing the PTAT and the CTAT currents and generating the bandgap reference voltage based on the sum of the currents. Equalizing includes connecting-across the terminals of the core a first fed-back amplifier with at least one first stage arranged as a folded setup and including first PMOS transistors arranged according to a common-gate setup. Equalizing also includes biasing the first stage based on the CTAT current. The summation of the PTAT and CTAT currents is performed in the feedback stage of the first amplifier.

Abstract translation: 根据实施例，产生可调节带隙参考电压包括产生与绝对温度（PTAT）成比例的电流。 产生PTAT电流包括跨越由PTAT电流穿过的芯的端子的均衡电压。 生成可调节带隙基准还包括产生与绝对温度（CTAT）成反比的电流​​，对PTAT和CTAT电流求和，并根据电流之和产生带隙基准电压。 均衡包括将核心的端子连接到具有布置为折叠设置的至少一个第一级的第一反馈放大器，并且包括根据公共门设置布置的第一PMOS晶体管。 均衡还包括基于CTAT电流偏置第一阶段。 在第一放大器的反馈级中执行PTAT和CTAT电流的求和。

公开(公告)号：US20150109861A1

公开(公告)日：2015-04-23

申请号：US14584165

申请日：2014-12-29

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francois Tailliet

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/10 ,  G06F11/167 ,  G06F11/20 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3495 ,  G11C29/74

Abstract: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase.

Abstract translation: 用于管理非易失性存储器的方法可以包括将数据写入非易失性存储器的存储器平面的第一组的第一阶段，然后将相同数据写入同一存储器的第二组的第二阶段 在第一写入阶段成功的情况下，非易失性存储器的平面。

公开(公告)号：US09006897B2

公开(公告)日：2015-04-14

申请号：US14148884

申请日：2014-01-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Antonio Di-Giacomo

IPC: H01L23/48 ,  H01L29/84 ,  H01L23/528 ,  H05K7/02 ,  B81C1/00

CPC classification number: B81C1/00246 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/098 ,  B81C2203/0136 ,  B81C2203/0145 ,  B81C2203/0714 ,  B81C2203/0735 ,  H01L23/528 ,  H01L2924/0002 ,  H05K7/02 ,  H01L2924/00

Abstract: An integrated circuit includes a number of metallization levels separated by an insulating region disposed over a substrate. A housing includes walls formed from metal portions produced in various metallization levels. A metal device is housed in the housing. An aperture is produced in at least one wall of the housing. An external mechanism outside of the housing is configured so as to form an obstacle to diffusion of a fluid out of the housing through the at least one aperture. At least one through-metallization passes through the external mechanism and penetrates into the housing through the aperture in order to make contact with at least one element of the metal device.

Abstract translation: 集成电路包括由布置在衬底上的绝缘区域分开的多个金属化水平。 壳体包括由各种金属化水平产生的金属部分形成的壁。 金属装置容纳在壳体中。 在壳体的至少一个壁中产生孔。 壳体外部的外部机构构造成阻止流体从壳体扩散通过至少一个孔。 至少一个贯穿金属化通过外部机构并穿过该孔穿透到外壳中，以便与金属装置的至少一个元件接触。

公开(公告)号：US20140366135A1

公开(公告)日：2014-12-11

申请号：US14299943

申请日：2014-06-09

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Yannick Teglia

IPC: G06F21/55

CPC classification number: G06F21/55 ,  G06F7/58 ,  G06F21/556

Abstract: A method for detecting a fault injection in a random number generation circuit, wherein a bit pattern is mixed to a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mix.

Abstract translation: 一种用于检测随机数生成电路中的故障注入的方法，其中将位模式混合到源自噪声源的比特流，并且在混合下游采样的信号中检测到该模式的存在。

公开(公告)号：US08901634B2

公开(公告)日：2014-12-02

申请号：US13786213

申请日：2013-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Yoann Goasduff ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L29/788 ,  G11C16/04 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/7889 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11524 ,  H01L29/66825

Abstract: The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.

Abstract translation: 本公开涉及一种集成电路，其包括形成在半导体衬底中的至少两个存储单元和与存储单元的选择晶体管共同的掩埋栅极。 掩埋栅极具有在选择晶体管的垂直沟道区域的前面延伸的第一深度的第一部分，以及大于深入埋入源极线的第一深度的至少第二深度的第二部分。 掩埋栅极的下侧由形成选择晶体管的源极区域的掺杂区域界定，并且在埋入栅极的第二部分穿入埋入源极线的水平面到达掩埋源极线，由此源极区域 耦合到埋地源线。