公开(公告)号：US20190279707A1

公开(公告)日：2019-09-12

申请号：US16351773

申请日：2019-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek PATHAK ,  Tanmoy ROY ,  Shishir KUMAR

IPC: G11C11/412 ,  G11C7/14 ,  G11C11/419

Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

公开(公告)号：US20190273484A1

公开(公告)日：2019-09-05

申请号：US16296094

申请日：2019-03-07

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Alok Kumar TRIPATHI ,  Amit VERMA ,  Anuj GROVER ,  Deepak Kumar BIHANI ,  Tanmoy ROY ,  Tanuj AGRAWAL

IPC: H03K3/3562 ,  G11C29/00

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

公开(公告)号：US20190266784A1

公开(公告)日：2019-08-29

申请号：US16280963

申请日：2019-02-20

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal SINGH ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06T15/08 ,  G06N3/08 ,  G06K9/00 ,  G06T7/62 ,  G06F9/38 ,  G06F16/901 ,  G06K9/62 ,  G06T7/11

Abstract: Embodiments of a device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and a data volume sculpting unit, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting unit has a counter, a comparator, and a controller. The data volume sculpting unit is arranged to receive a stream of feature map data that forms a three-dimensional (3D) feature map. The 3D feature map is formed as a plurality of two-dimensional (2D) data planes. The data volume sculpting unit is also arranged to identify a 3D volume within the 3D feature map that is dimensionally smaller than the 3D feature map and isolate data from the 3D feature map that is within the 3D volume for processing in a deep learning algorithm.

公开(公告)号：US10393804B2

公开(公告)日：2019-08-27

申请号：US16170479

申请日：2018-10-25

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/3177 ,  G01R31/3193 ,  G06F11/26 ,  G06F11/25 ,  G06F11/27 ,  G01R31/317 ,  G01R31/319

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

公开(公告)号：US20190227096A1

公开(公告)日：2019-07-25

申请号：US16257694

申请日：2019-01-25

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Mahesh CHOWDHARY ,  Arun KUMAR ,  Ghanapriya SINGH ,  Rajendar BAHL

IPC: G01P15/00 ,  G06F1/16 ,  G01P15/18 ,  G06K9/62 ,  G06N20/10 ,  G10L21/10 ,  H04W4/029

Abstract: A distributed computing system for artificial intelligence in autonomously appreciating a circumstance context of a smart device. Raw context data is detected by sensors associated with the smart device. The raw context data is pre-processed by the smart device and then provided to a cloud based server for further processing. At the cloud based server, various sets of feature data are obtained from the pre-processed context data. The various sets of feature data are compared with corresponding classification parameters to determine a classification of a continuous event and/or a classification of transient event, if any, which occur in the context. The determined classification of the continuous event and the transient event will be used to autonomously configure the smart device or another related smart device to fit the context.

公开(公告)号：US10348314B2

公开(公告)日：2019-07-09

申请号：US15888153

申请日：2018-02-05

Applicant: STMicroelectronics International N.V.

Inventor： Anand Kumar ,  Gagan Midha

IPC: H03L7/089 ,  H03C3/09 ,  H03L7/093 ,  H03L7/099 ,  H03L7/197 ,  H04B15/04

Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

公开(公告)号：US20190158858A1

公开(公告)日：2019-05-23

申请号：US16251798

申请日：2019-01-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Sumit Johar ,  Surinder Pal Singh

IPC: H04N19/433

Abstract: Video encoders and decoders and video encoding and decoding methods are provided. A video encoder includes an input buffer configured to receive a video data stream and to supply current frame data, a frame buffer configured to store reconstructed frame data, and an encoder circuit configured to read reference frame data from the frame buffer, to encode the current frame data received from the input buffer using the reference frame data and to write the reconstructed frame data to the frame buffer. The encoder circuit may be configured to write the reconstructed frame data by overwriting the reference frame data in the frame buffer.

公开(公告)号：US10284201B1

公开(公告)日：2019-05-07

申请号：US15877970

申请日：2018-01-23

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas Rana

IPC: H03L5/00 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185

Abstract: A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.

公开(公告)号：US20190129790A1

公开(公告)日：2019-05-02

申请号：US15798916

申请日：2017-10-31

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Abhishek Gupta

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/10 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  H04L1/0045 ,  H04L1/0063 ,  H04L1/0082

Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

公开(公告)号：US20190128960A1

公开(公告)日：2019-05-02

申请号：US15797504

申请日：2017-10-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tejinder KUMAR ,  Akshat JAIN

IPC: G01R31/317 ,  G01R31/3177

Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.