公开(公告)号：US10121787B2

公开(公告)日：2018-11-06

申请号：US15706760

申请日：2017-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/82 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: Method for fabricating Fin field effect transistors (FinFETs) are disclosed. One of the methods includes the following steps. A first semiconductor fin, a second semiconductor fin and an insulator between the first semiconductor fin and the second semiconductor fin are formed. A first dummy gate, a second dummy gate and an opening between the first and second dummy gates are formed over the insulator, wherein the first dummy gate and the second dummy gate cross over portions of the first semiconductor fin and the second semiconductor fin respectively. A dielectric layer is formed in the opening, wherein the dielectric layer comprises an air gap therein. The first dummy gate and the second dummy gate are replaced with a first gate and a second gate, wherein the first gate and the second gate are electrically insulated by the dielectric layer comprising the air gap therein.

公开(公告)号：US10096712B2

公开(公告)日：2018-10-09

申请号：US15002287

申请日：2016-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/82 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/67 ,  G01N21/88

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The method includes the steps of: forming a plurality of fins supported by a substrate; depositing a gate layer on the fins; and etching the gate layer by plasma etching with an etching gas to form a gate having two notch features. The etching gas is supplied at a ratio of a flow rate at a center area of the substrate to a flow rate at a periphery area of the substrate in a range from 0.2 to 1. The disclosure also provides a method of monitoring a quality of the FinFET device, the method comprising: measuring a profile of the notch feature; and obtaining the quality of the FinFET device by comparing the profile of the notch feature with a predetermined criterion.

公开(公告)号：US10032914B2

公开(公告)日：2018-07-24

申请号：US14887873

申请日：2015-10-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, an insulating structure, and a gate stack. The substrate has at least one semiconductor fin. The insulating structure is disposed above the substrate and separated from the semiconductor fin to form a gap therebetween. The insulating structure has a sidewall facing the semiconductor fin. The gate stack covers at least a portion of the semiconductor fin and is at least disposed in the gap between the insulating structure and the semiconductor fin. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer covers the semiconductor fin while leaves the sidewall of the insulating structure uncovered. The gate electrode is disposed above the high-κ dielectric layer and at least in the gap between the insulating structure and the semiconductor fin.

公开(公告)号：US20180174956A1

公开(公告)日：2018-06-21

申请号：US15891394

申请日：2018-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L29/06 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/53295 ,  H01L29/0649 ,  H01L2221/1031

Abstract: A method for manufacturing an interconnect structure is provided, and the method is as below. A dielectric layer is deposited over a substrate. The dielectric layer is etched to form a recess. A dummy adhesion layer is deposited on sidewalls of the recess. A conductive layer is formed in the recess. The dummy adhesion layer is removed to expose a portion of the conductive layer.

公开(公告)号：US09991285B2

公开(公告)日：2018-06-05

申请号：US14067424

申请日：2013-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Che-Cheng Chang ,  Chang-Yin Chen ,  Jr-Jung Lin ,  Chih-Han Lin ,  Yung-Jung Chang

IPC: H01L27/12 ,  H01L21/3213 ,  H01L27/088 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L27/1211 ,  H01L21/32137 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

公开(公告)号：US09923070B2

公开(公告)日：2018-03-20

申请号：US15051595

申请日：2016-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/76 ,  H01L29/417 ,  H01L29/40 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/41775 ,  H01L21/28512 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure.

公开(公告)号：US09917176B2

公开(公告)日：2018-03-13

申请号：US15297105

申请日：2016-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L21/764 ,  H01L29/40

CPC classification number: H01L29/66795 ,  H01L21/02271 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/7851

Abstract: A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate. Two cells adjacent to each other are formed on the semiconductor fin. A gate conductor is formed on a top of the semiconductor fin at a common boundary that is shared by the two cells. A gate spacer is formed to peripherally enclose the gate conductor. The gate conductor and the semiconductor fin are etched to form an air gap, thereby dividing the semiconductor fin into two portions of the semiconductor fin. A dielectric cap layer is deposited into the air gap to cap a top of the air gap.

公开(公告)号：US09911645B2

公开(公告)日：2018-03-06

申请号：US15394620

申请日：2016-12-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/785

Abstract: A method includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The method includes an adhesion layer formed in the dielectric layer and over the first metal layer, and the adhesion layer is a discontinuous layer. The method includes a second metal layer formed in the dielectric layer, and the adhesion layer is formed between the second metal layer and the dielectric layer. The second metal layer includes a via portion and a trench portion over the via portion, and the trench portion is wider than the via portion.

公开(公告)号：US09876115B2

公开(公告)日：2018-01-23

申请号：US14935115

申请日：2015-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/0228 ,  H01L21/3065 ,  H01L21/32135 ,  H01L21/76243 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has a dielectric portion extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The dielectric portion divides the semiconductor fin into two portions of the semiconductor fin.

公开(公告)号：US09837536B2

公开(公告)日：2017-12-05

申请号：US15208377

申请日：2016-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L27/092 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat area, and the flat area extends in the second direction and the third direction.