Abstract:
An amplifier device with gain switching includes an amplifier, and a configurable load circuit including an inductive element. The configurable load circuit is capable of exhibiting two configurations having two different impedance values. A controllable switch is connected between the amplifier and the load circuit to select one of the two configurations of the load circuit. The load circuit includes two insulated-gate field effect load transistors connected in series, and which operate in a triode mode. The inductive element is connected in parallel with the pair of load transistors, and between a power supply terminal and the switching circuit.
Abstract:
Disclosed is a device to control a circuit for the vertical deflection of a spot scanning a screen, and more particularly a control device whose output amplifier stage works in class D mode at the rate of a switching signal called a first switching signal. The control device has an internal auxiliary supply to generate the overvoltage needed for the fast flyback of the spot. This auxiliary power supply is a switching voltage generation circuit whose switching signal, called a second switching signal, is synchronous with the first switching signal. The present invention has been shown to used advantageously in television screens and/or computer screens.
Abstract:
Before a predetermined processing sequence, the integrated circuit detects the state of at least one timer. The circuit controls the activation of the timer if it is not activated, and disables itself if the timer is activated.
Abstract:
A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing units. The processor core is clocked by a clock signal. A branching instruction received by the central unit, in the course of a current cycle, is processed in the course of the current cycle.
Abstract:
The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.
Abstract:
An electromagnetic transponder including an oscillating circuit adapted to extracting from a radiating field a high-frequency amplitude-modulated signal, circuitry for extracting from said high-frequency signal an approximately D.C. supply voltage, a demodulator of data carried by the high-frequency signal, and circuitry for separately regulating the supply voltage and a useful voltage carrying the data.
Abstract:
An injection-molding mold having two parts adapted to take up between them the periphery of a substrate and one of which defines a molding cavity connected to means for feeding a coating material for encapsulating a row of spaced integrated circuit chips carried by a mounting face of said substrate and placed in said cavity, characterized in that the part (10) with cavities (14) includes a slot (17) for injecting the coating material into said cavity above the mounting face (2) of the substrate, recessed into its face (12) bearing on the substrate (1) along said row of chips and extending approximately the whole length of that row of chips.
Abstract:
An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.
Abstract:
A pair of complementary current sources includes a reference current source, and two complementary current mirrors having the same number of branches provided with bipolar mirror transistors. The bases of the mirror transistors of the complementary mirrors are connected to a common node. One of the complementary mirrors is connected to the reference source. An intermediate current mirror includes a first slave branch connected to the other complementary current mirror, a second slave branch connected to the reference source, and a master branch connected to the output of a trimming circuit for trimming the complementary currents for substantially equalizing the base currents of the mirror transistors of the complementary current mirrors. The input of the trimming circuit is connected to the common node.
Abstract:
A generator producing a clock signal whose frequency depends on a control voltage includes a comparator for comparing a period of the clock signal with a desired period, and for providing at least one first control signal based upon the comparison. The generator includes a sampler circuit for sampling the first control signal, and for producing a first sampled control signal. The generator also includes a voltage generator for providing the variable control voltage as a function of the first sampled control signal.