公开(公告)号：US11824008B2

公开(公告)日：2023-11-21

申请号：US17956761

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

CPC classification number: H01L23/5385 ,  H01L23/13 ,  H01L23/5381 ,  H01L24/14 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L21/6835 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/49175 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0401 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/00011 ,  H01L2224/0401

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US11756948B2

公开(公告)日：2023-09-12

申请号：US16400768

申请日：2019-05-01

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Aleksandar Aleksov ,  Henning Braunisch

IPC: H01L27/01 ,  H01L21/47 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L27/016 ,  H01L21/47 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/75

Abstract: Embodiments described herein are directed to a thin film capacitor (TFC) for power delivery that is in situ in a package substrate and techniques of fabricating the TFC. In one example, the TFC includes a first electrode, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. Each of the dielectric layer and the second electrode comprises an opening. Furthermore, the two openings are positioned over one another such that the openings expose a surface of the first electrode. In this example, a first vertical interconnect access (via) is positioned on the exposed surface of the first electrode and a second via is positioned on an exposed surface of the second electrode. The TFC can be positioned in or on a layer of the package substrate close to a component (e.g., a die, a die stack, etc.) on the package substrate that may require a decoupling capacitance.

公开(公告)号：US11751367B2

公开(公告)日：2023-09-05

申请号：US17468510

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Feras Eid

IPC: H05K9/00 ,  H01L23/60 ,  H01L21/48 ,  C08G61/12 ,  C08G73/06 ,  C08G85/00 ,  H01L23/498

CPC classification number: H05K9/0079 ,  C08G61/126 ,  C08G73/0611 ,  C08G85/004 ,  H01L21/4867 ,  H01L23/60 ,  C08G2261/1424 ,  C08G2261/3223 ,  C08G2261/514 ,  C08G2261/78 ,  H01L23/498

Abstract: Embodiments may relate to a microelectronic package comprising: a die and a package substrate coupled to the die with a first interconnect on a first face. The package substrate comprises: a second interconnect and a third interconnect on a second face opposite to the first face; a conductive signal path between the first interconnect and the second interconnect; a conductive ground path between the second interconnect and the third interconnect; and an electrostatic discharge (ESD) protection material coupled to the conductive ground path. The ESD protection material comprises a first electrically-conductive carbon allotrope having a first functional group, a second electrically-conductive carbon allotrope having a second functional group, and an electrically-conductive polymer chemically bonded to the first functional group and the second functional group permitting an electrical signal to pass between the first and second electrically-conductive carbon allotropes.

公开(公告)号：US20230198058A1

公开(公告)日：2023-06-22

申请号：US17556784

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Telesphor Kamgaing ,  Neelam Prabhu Gaunkar ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Brandon Rawlings

IPC: H01M50/117 ,  H01L23/58

CPC classification number: H01M50/117 ,  H01L23/58

Abstract: Embedded batteries within glass cores are disclosed. Example apparatus include a glass core layer having opposing first and second surfaces, the glass core layer including a cavity extending from the first surface toward the second surface, and a battery including a first conductive material positioned in the cavity, a second conductive material positioned in the cavity, and an electrolyte to separate the first conductive material from the second conductive material.

公开(公告)号：US20230098710A1

公开(公告)日：2023-03-30

申请号：US17484329

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Aleksandar Aleksov ,  Feras Eid ,  Adel Elsherbini ,  Wenhao Li ,  Stephen Morein

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

公开(公告)号：US20230098303A1

公开(公告)日：2023-03-30

申请号：US17484339

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Aleksandar Aleksov ,  Feras Eid ,  Adel Elsherbini ,  Wenhao Li ,  Stephen Morein

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/498 ,  H01L21/768

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

公开(公告)号：US20230096368A1

公开(公告)日：2023-03-30

申请号：US17485243

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel Elsherbini ,  Johanna Swan ,  Feras Eid ,  Thomas L. Sounart ,  Henning Braunisch ,  Beomseok Choi ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  William J. Lambert

IPC: H01L49/02 ,  H01F27/255 ,  H01F27/28 ,  H01F41/04 ,  H01F41/02 ,  H01L23/498 ,  H01L23/64 ,  H01L21/48

Abstract: An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.

公开(公告)号：US20230095063A1

公开(公告)日：2023-03-30

申请号：US17484286

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  William J. Lambert ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini ,  Henning Braunisch ,  Stephen Morein ,  Aleksandar Aleksov ,  Feras Eid

IPC: G05F1/44 ,  H01L23/50 ,  H01L25/065

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US20220415853A1

公开(公告)日：2022-12-29

申请号：US17358948

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Johanna Swan ,  Shawna Liff ,  Feras Eid ,  Adel Elsherbini ,  Julien Sebot

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A composite integrated circuit (IC) structure includes at least a first IC die in a stack with a second IC die. Each die has a device layer and metallization layers interconnected to transistors of the device layer and terminating at features. First features of the first IC die are primarily of a first composition with a first microstructure. Second features of the second IC die are primarily of a second composition or a second microstructure. A first one of the second features is in direct contact with one of the first features. The second composition has a thermal conductivity at least an order of magnitude lower than that of the first composition and first microstructure. The first composition may have a thermal conductivity at least 40 times that of the second composition or second microstructure.

公开(公告)号：US11532584B2

公开(公告)日：2022-12-20

申请号：US17098754

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Sri Ranga Sai Boyapati ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Javier Soto Gonzalez ,  Kwangmo Chris Lim ,  Aleksandar Aleksov

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/13 ,  H01L21/48 ,  H01L25/065

Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.