公开(公告)号：US20230186427A1

公开(公告)日：2023-06-15

申请号：US17561267

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Linwei Yu ,  Jiangli Ye ,  Yang Ling ,  Hui Zhou

IPC: G06T3/40 ,  G06T11/00 ,  G06V10/56

CPC classification number: G06T3/4015 ,  G06T11/001 ,  G06V10/56

Abstract: A method and processing device for image demosaicing is provided. The processing device comprises memory and a processor. The processor is configured to, for a pixel of a Bayer image which filters an acquired image using three color components, determine directional color difference weightings in a horizontal direction and a vertical direction, determine a color difference between the first color component and the second color component and a color difference between the second color component and the third color component based on the directional color difference weightings, interpolate a color value of the pixel from the one color component and the color differences and provide a color image for display.

公开(公告)号：US20230186084A1

公开(公告)日：2023-06-15

申请号：US18050939

申请日：2022-10-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Song Zhang ,  Jiantan Liu ,  Hua Zhang ,  Min Yu

IPC: G06N3/08 ,  G06N3/04 ,  G06F18/21 ,  G06V10/82 ,  G06V10/44 ,  G06V10/50 ,  G06V10/94

CPC classification number: G06N3/08 ,  G06N3/04 ,  G06F18/217 ,  G06V10/82 ,  G06V10/454 ,  G06V10/449 ,  G06V10/50 ,  G06V10/955

Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.

公开(公告)号：US20230185575A1

公开(公告)日：2023-06-15

申请号：US17550878

申请日：2021-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony Thomas Gutierrez ,  Karthik Ramu Sangaiah ,  Vedula Venkata Srikant Bharadwaj

IPC: G06F9/38 ,  G06F9/30 ,  G06F1/18

CPC classification number: G06F9/3853 ,  G06F9/3885 ,  G06F9/30145 ,  G06F1/189

Abstract: VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very long instruction word machine and operations for execution by the very long instruction word machine is obtained. A power setting of the very long instruction word machine is adjusted based on the power configuration of the instruction, and the operations of the instruction are executed by the very long instruction word machine.

公开(公告)号：US11676924B2

公开(公告)日：2023-06-13

申请号：US17195046

申请日：2021-03-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Milind S. Bhagavat ,  Lei Fu

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/10145 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13026 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13172 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2924/014 ,  H01L2924/381

Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.

公开(公告)号：US20230176847A1

公开(公告)日：2023-06-08

申请号：US17545801

申请日：2021-12-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Amit Ben-Moshe ,  Ian Charles Colbert

IPC: G06F8/65 ,  G06T15/00 ,  G06F8/41 ,  G06F8/51 ,  G06N20/00

CPC classification number: G06F8/65 ,  G06T15/005 ,  G06F8/443 ,  G06F8/51 ,  G06N20/00

Abstract: Shader source code performance prediction is described. In accordance with the described techniques, an update to shader source code for implementing a shader is received. A prediction of performance of the shader on a processing unit is generated based on the update to the shader source code. Feedback about the update is output. The feedback includes the prediction of performance of the shader. In one or more implementations, generating the prediction of performance of the shader includes compiling the shader source code with the update to generate a representation of the shader, inputting the representation of the shader to one or more machine learning models, and receiving the prediction of performance of the shader as an output from the one or more machine learning models.

公开(公告)号：US20230176786A1

公开(公告)日：2023-06-08

申请号：US17850658

申请日：2022-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron John Nygren ,  Karthik Gopalakrishnan ,  Tsun Ho Liu

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0671

Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.

公开(公告)号：US11669457B2

公开(公告)日：2023-06-06

申请号：US17459100

申请日：2021-08-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul James Moyer ,  Douglas Benson Hunt

IPC: G06F12/0891 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811

CPC classification number: G06F12/0891 ,  G06F9/3009 ,  G06F9/3816 ,  G06F12/0811

Abstract: Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.

公开(公告)号：US20230161618A1

公开(公告)日：2023-05-25

申请号：US17530936

申请日：2021-11-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael L. Golden ,  Paul Blinzer ,  Magiting M. Talisayon ,  Srikanth Masanam ,  Ripal Butani ,  Upasanah Swaminathan

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/482

Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

公开(公告)号：US11657014B2

公开(公告)日：2023-05-23

申请号：US17115384

申请日：2020-12-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jason R. Talbert

IPC: G06F13/40 ,  G06F13/20 ,  G06F9/4401

CPC classification number: G06F13/4027 ,  G06F13/20 ,  G06F9/4405 ,  G06F2213/40

Abstract: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.

公开(公告)号：US11656877B2

公开(公告)日：2023-05-23

申请号：US17219775

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Maxim V. Kazakov

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/30152 ,  G06F9/3851 ,  G06F9/3869

Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.