公开(公告)号：US20030102474A1

公开(公告)日：2003-06-05

申请号：US10004755

申请日：2001-12-03

Applicant: ProMOS Technologies Inc.

Inventor： Ting-Sing Wang

IPC: H01L023/58

CPC classification number: H01L22/34

Abstract: The present invention provides a semiconductor device for detecting gate defects and the method of using the same to detect gate defects. The semiconductor device is comprised of a semiconductor substrate having an oxide layer on the top, a gate having spacers, formed on the oxide layer and surrounding the semiconductor substrate, wherein the gate is also patterned to divide the semiconductor substrate into two parts not electrically connected, and a conductive layer formed on the semiconductor outside the gate. In addition, the method for using the semiconductor device of the present invention to detect gate defects is comprised of applying a ground voltage and a set voltage respectively to two parts divided by the gate in the semiconductor device, and measuring current between the two parts.

Abstract translation: 本发明提供一种用于检测栅极缺陷的半导体器件及其使用该方法来检测栅极缺陷。 半导体器件由在顶部具有氧化物层的半导体衬底，形成在氧化物层上并包围半导体衬底的间隔物的栅极组成，其中栅极也被图案化以将半导体衬底分成两个部分而不是电连接 以及形成在栅极外部的半导体上的导电层。 此外，使用本发明的半导体器件来检测栅极缺陷的方法包括分别将接地电压和设定电压施加到由半导体器件中的栅极划分的两个部分以及测量两个部分之间的电流。

公开(公告)号：US20030059996A1

公开(公告)日：2003-03-27

申请号：US10060590

申请日：2002-01-30

Applicant: ProMos Technologies Inc.

Inventor： Nien-Yu Tsai ,  Yung-Ching Wang

IPC: H01L021/8238

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/823425 ,  H01L21/823475

Abstract: A method for forming a gate structure is provided. The forming method includes steps of providing a semiconductor substrate; forming an insulation layer, a first gate conductor layer, a second gate conductor layer, and a masking layer on the semiconductor substrate; removing portions of the masking layer, the semiconductor substrate, and the first gate conductor layer to define the gate structure by etching; executing a cleaning process to the semiconductor with a specific cleaning agent for etching the second gate conductor layer, thereby removing portions of the second gate conductor layer in the gate structure; and performing a thermal treatment process to the semiconductor substrate and forming an insulation spacer on the side surface of the gate structure.

Abstract translation: 提供一种形成栅极结构的方法。 成形方法包括提供半导体衬底的步骤; 在半导体衬底上形成绝缘层，第一栅极导体层，第二栅极导体层和掩模层; 去除掩模层，半导体衬底和第一栅极导体层的部分，以通过蚀刻限定栅极结构; 利用用于蚀刻第二栅极导体层的特定清洁剂对半导体执行清洁处理，从而去除栅极结构中的第二栅极导体层的部分; 对所述半导体基板进行热处理，在所述栅极结构的侧面形成绝缘间隔物。

公开(公告)号：US6156597A

公开(公告)日：2000-12-05

申请号：US94347

申请日：1998-06-09

Applicant: Wen-Ping Yen ,  Chia-Lin Ku ,  Chong-Che Lee

Inventor： Wen-Ping Yen ,  Chia-Lin Ku ,  Chong-Che Lee

IPC: H01L21/316 ,  H01L21/334 ,  H01L21/8242

CPC classification number: H01L29/66181 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612

Abstract: A method of fabricating a semiconductor device is provided including the steps of:(a) forming one or more protrusions on a semiconductor surface,(b) forming a first O.sub.x /TEOS film on top and side surfaces of the protrusions and surface area portions of the semiconductor surface separating the protrusions from each other, if any, and(c) forming a second O.sub.3 /TEOS film on, and covering, the first film.Illustratively, the protrusions have nitride regions at their peaks. The first film can be a low pressure (e.g., 30-70 torr) O.sub.3 /TEOS film or a plasma enhanced chemical vapor deposition (PECVD) O.sub.2 /TEOS film. The second film is a high pressure (e.g., 200-600 torr) O.sub.3 /TEOS film.The high pressure O.sub.3 /TEOS film avoids all of the disadvantages of the prior art. The low pressure O.sub.3 /TEOS film or PECVD O.sub.2 /TEOS film covers the nitride region of the protrusion so that the high pressure O.sub.3 /TEOS film will continuously cover the entire structure with a uniform thickness.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤：（a）在半导体表面上形成一个或多个突起，（b）在凸起和表面区域的顶部和侧表面上形成第一Ox / TEOS膜 所述半导体表面将所述突起彼此分离（如果有的话），和（c）在所述第一膜上形成第二O 3 / TEOS膜并覆盖所述第一膜。 示例性地，突起在其峰处具有氮化物区域。 第一膜可以是低压（例如，30-70托）O 3 / TEOS膜或等离子体增强化学气相沉积（PECVD）O 2 / TEOS膜。 第二个膜是高压（例如，200-600托）O 3 / TEOS膜。 高压O3 / TEOS膜避免了现有技术的所有缺点。 低压O3 / TEOS膜或PECVD O2 / TEOS膜覆盖突起的氮化物区域，使得高压O 3 / TEOS膜将以均匀的厚度连续覆盖整个结构。

公开(公告)号：US06110812A

公开(公告)日：2000-08-29

申请号：US309934

申请日：1999-05-11

Applicant: Chiao-Lin Ho ,  J. S. Shiao

Inventor： Chiao-Lin Ho ,  J. S. Shiao

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/44

CPC classification number: H01L21/28061 ,  H01L29/4933

Abstract: A method for forming a polycide-gate structure is disclosed. The method comprises forming a gate oxide layer on a substrate. Then a polysilicon layer is formed on the gate oxide layer. Next a silicide layer is formed over the polysilicon layer. Thereafter, an amorphous silicon layer is formed on the silicide layer. Then, the amorphous silicon layer, the silicide layer, the polysilicon layer and the gate oxide layer are patterned and etched to define a gate region by using a photoresist mask. Source/drain regions are formed using the gate region as an implant mask. Finally, a cap silicon nitride layer is formed over the amorphous silicon layer.

Abstract translation: 公开了一种形成多晶硅栅极结构的方法。 该方法包括在衬底上形成栅氧化层。 然后在栅极氧化物层上形成多晶硅层。 接下来，在多晶硅层上形成硅化物层。 此后，在硅化物层上形成非晶硅层。 然后，通过使用光致抗蚀剂掩模，对非晶硅层，硅化物层，多晶硅层和栅极氧化物层进行图案化和蚀刻以限定栅极区域。 使用栅极区域作为植入掩模形成源极/漏极区域。 最后，在非晶硅层上形成帽状氮化硅层。

公开(公告)号：US07932565B2

公开(公告)日：2011-04-26

申请号：US12193502

申请日：2008-08-18

Applicant: Hsiao Che Wu ,  Wen Li Tsai

Inventor： Hsiao Che Wu ,  Wen Li Tsai

IPC: H01L21/70

CPC classification number: H01L21/76232 ,  H01L21/7624 ,  H01L21/76264 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

Abstract translation: 集成电路结构包括半导体衬底，位于半导体衬底中的器件区域，与器件区域相邻的绝缘区域，位于绝缘区域中的隔离结构，其包括瓶部分和填充有电介质材料的颈部， 以及夹在器件区域和绝缘区域之间的电介质层。

公开(公告)号：US07851253B2

公开(公告)日：2010-12-14

申请号：US12292508

申请日：2008-11-20

Applicant: Wei-Su Chen

Inventor： Wei-Su Chen

IPC: H01L45/00

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/148 ,  H01L45/1691

Abstract: A phase change memory device is provided. The phase change memory device includes a substrate with a first electrode layer formed thereon. A first phase change memory structure is on the first electrode layer and electrically connected to the first electrode layer. A second phase change memory structure is on the first phase change memory structure and electrically connected to the first phase change memory structure, wherein the first or second phase change memory structure includes a cup-shaped heating electrode. A first insulating layer covers a portion of the cup-shaped heating electrode along a first direction. A first electrode structure covers a portion of the first insulating layer and the cup-shaped heating electrode along a second direction. The first electrode structure includes a pair of phase change material sidewalls on a pair of sidewalls of the first electrode structure and covering a portion of the cup-shaped heating electrode.

Abstract translation: 提供了相变存储器件。 相变存储器件包括其上形成有第一电极层的基板。 第一相变存储器结构在第一电极层上并且电连接到第一电极层。 第二相变存储器结构位于第一相变存储器结构上并电连接到第一相变存储器结构，其中第一或第二相变存储器结构包括杯形加热电极。 第一绝缘层沿着第一方向覆盖杯形加热电极的一部分。 第一电极结构沿第二方向覆盖第一绝缘层和杯形加热电极的一部分。 第一电极结构包括在第一电极结构的一对侧壁上的一对相变材料侧壁，并覆盖杯形加热电极的一部分。

公开(公告)号：US07764555B2

公开(公告)日：2010-07-27

申请号：US12173823

申请日：2008-07-16

Applicant: Chung-Yuan Chang ,  Ming Hsieh Tsai ,  Che-Yi Hsu ,  Yuan-Hwa Lee

Inventor： Chung-Yuan Chang ,  Ming Hsieh Tsai ,  Che-Yi Hsu ,  Yuan-Hwa Lee

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C11/401 ,  G11C29/025 ,  G11C29/50016 ,  G11C2029/1202

Abstract: A leakage testing method for a DRAM having a recess gate is provided. The method includes the steps of: programming to set the first storage unit and the second storage unit of a same memory cell with different storage statuses; and disturbing one of the word lines extending through the memory cells; then determining whether the DRAM is acceptable or not. When another one of the word lines extending through the memory cells is caused with a reading error by disturbing the one of the word lines extending through the memory cells, a failure is determined as occurred, and the failure is attributed to a leakage type of extended depletion region. When the another one of the word lines extending through the memory cells is not caused with a reading error by disturbing the one of the word lines extending through the memory cells, the DRAM is determined as acceptable.

Abstract translation: 提供了具有凹槽的DRAM的漏电检测方法。 该方法包括以下步骤：对具有不同存储状态的相同存储单元的第一存储单元和第二存储单元进行编程; 并扰乱延伸通过存储器单元的字线之一; 然后确定DRAM是否可接受。 当延伸通过存储单元的另一个字线通过干扰延伸通过存储器单元的字线之一而引起读取误差时，确定发生故障，并且故障归因于扩展的泄漏类型 耗尽区。 当延伸通过存储单元的字线中的另一条字线不是通过干扰延伸通过存储单元的字线之一而引起读取误差时，DRAM被确定为可接受的。

公开(公告)号：US07729183B2

公开(公告)日：2010-06-01

申请号：US12147012

申请日：2008-06-26

Applicant: Ling Wen Hsiao

Inventor： Ling Wen Hsiao

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

Abstract: A data sensing method for a dynamic random access memory including a storage capacitor configured to store data, a bit line, a transistor connecting the storage capacitor and the bit line, a reference bit line, and a sense amplifier connecting the bit line and the reference bit line. The data sensing method comprises the steps of turning off the transistor when the stored data is a predetermined value before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line, and turning on the transistor when the stored data is opposite to the predetermined value such that a charge sharing process occurs between the storage capacitor and a parasitic capacitor of the bit line before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line.

Abstract translation: 一种用于动态随机存取存储器的数据感测方法，包括配置为存储数据的存储电容器，位线，连接存储电容器和位线的晶体管，参考位线和连接位线和参考电压的读出放大器 位线。 数据检测方法包括以下步骤：当存储的数据是预定值时，在使读出放大器感测位线和参考位线的电压之前关断晶体管，并且当存储的数据相反时，接通晶体管 达到预定值，使得在使读出放大器感测位线和参考位线的电压之前，在存储电容器和位线的寄生电容器之间发生电荷共享处理。

公开(公告)号：US07679075B2

公开(公告)日：2010-03-16

申请号：US12020494

申请日：2008-01-25

Applicant: Te-Sheng Chao

Inventor： Te-Sheng Chao

IPC: H01L47/00

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  Y10S438/90

Abstract: A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at different layers.

Abstract translation: 公开了一种相变存储器阵列，其包括具有图案化相变层的第一单元和具有图案化相变层的第二单元，其中第一单元的图案化相变层和第二单元的图案化相变层 被布置在不同的层。

公开(公告)号：US07675054B2

公开(公告)日：2010-03-09

申请号：US12016093

申请日：2008-01-17

Applicant: Li-Shu Tu

Inventor： Li-Shu Tu

IPC: H01L29/04

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675

Abstract: Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer and electrically connected to the first conductive electrode. A space is disposed in the second dielectric layer to at least isolate a sidewall of the phase change material layer and the second dielectric layer adjacent thereto. A second conductive electrode is disposed in the second dielectric layer and electrically connected to the phase change material layer.

Abstract translation: 提供了相变存储器件及其制造方法。 相变存储器件包括设置在第一介电层中的第一导电电极。 第二介电层设置在第一介电层上。 相变材料层设置在第二电介质层中并与第一导电电极电连接。 在第二电介质层中设置空间以至少隔离相变材料层和与其相邻的第二电介质层的侧壁。 第二导电电极设置在第二电介质层中并电连接到相变材料层。