PROBES WITH FIDUCIAL MARKS, PROBE SYSTEMS INCLUDING THE SAME, AND ASSOCIATED METHODS

    公开(公告)号:US20170205443A1

    公开(公告)日:2017-07-20

    申请号:US14997371

    申请日:2016-01-15

    CPC classification number: G01R1/06794 G01R31/2891

    Abstract: Probes with fiducial marks, probe systems including the same, and associated methods. The probes include a beam portion and a probe tip that is configured to contact a device under test (DUT), and further include a fiducial mark formed on the beam portion that is configured to facilitate alignment of the probe and the DUT. The fiducial mark is configured to be visible to an optical assembly, and is in focus to the optical assembly within a depth of field of the optical assembly that is smaller than a depth of field over which the beam portion is in focus to the optical assembly. The methods include methods of utilizing and/or manufacturing the probes.

    SYSTEMS AND METHODS FOR ON-WAFER DYNAMIC TESTING OF ELECTRONIC DEVICES
    23.
    发明申请
    SYSTEMS AND METHODS FOR ON-WAFER DYNAMIC TESTING OF ELECTRONIC DEVICES 审中-公开
    电子设备的静态动态测试系统和方法

    公开(公告)号:US20150241472A1

    公开(公告)日:2015-08-27

    申请号:US14625385

    申请日:2015-02-18

    CPC classification number: G01R31/2601 G01R31/2889

    Abstract: Systems and methods for on-wafer dynamic testing of electronic devices. The systems include a probe head assembly, a probe-side contacting structure, a chuck, and a chuck-side contacting structure. The probe head assembly includes a probe configured to electrically contact a first side of a device under test (DUT). The probe-side contacting structure includes a probe-side contacting region. The chuck includes an electrically conductive support surface configured to support a substrate that includes the DUT and to electrically contact a second side of the DUT. The probe head assembly and the chuck are configured to translate relative to one another to selectively establish electrical contact between the probe and the DUT. The chuck-side contacting structure includes a chuck-side contacting region that is in electrical communication with the electrically conductive support surface and opposed to the probe-side contacting structure. The methods may include methods of operating the system or systems.

    Abstract translation: 电子器件晶圆动态测试的系统和方法。 该系统包括探针头组件,探针侧接触结构,卡盘和卡盘侧接触结构。 探头组件包括被配置为电接触被测器件(DUT)的第一侧的探针。 探针侧接触结构包括探针侧接触区域。 卡盘包括被配置为支撑包括DUT的基板并且电接触DUT的第二侧的导电支撑表面。 探针头组件和卡盘被配置为相对于彼此平移以选择性地建立探针和DUT之间的电接触。 卡盘侧接触结构包括与导电支撑表面电连通并与探针侧接触结构相对的卡盘侧接触区域。 这些方法可以包括操作系统或系统的方法。

    PROBER FOR TESTING DEVICES IN A REPEAT STRUCTURE ON A SUBSTRATE

    公开(公告)号:US20150008948A1

    公开(公告)日:2015-01-08

    申请号:US14491606

    申请日:2014-09-19

    CPC classification number: G01R1/073 G01R1/04 G01R31/2891

    Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.

    SYSTEMS AND METHODS FOR HANDLING SUBSTRATES AT BELOW DEW POINT TEMPERATURES
    26.
    发明申请
    SYSTEMS AND METHODS FOR HANDLING SUBSTRATES AT BELOW DEW POINT TEMPERATURES 有权
    用于在下面的点温度处理基板的系统和方法

    公开(公告)号:US20140185649A1

    公开(公告)日:2014-07-03

    申请号:US14141781

    申请日:2013-12-27

    CPC classification number: G01N25/66 G01R31/00 G01R31/2862

    Abstract: Disclosed systems and methods for testing a device under test (DUT) with a probe system are selected to test a DUT at a temperature below the dew point of the ambient environment surrounding the probe system. Probe systems include a measurement chamber configured to isolate a cool, dry testing environment and a measurement chamber door configured to selectively isolate the internal volume of the measurement chamber. When a DUT, that is or is included on a substrate, is tested at a low temperature, systems and methods are selected to heat the substrate in a dry environment, at least partially isolated from the measurement chamber, to at least a temperature above the dew point and/or the frost point of the ambient environment.

    Abstract translation: 选择用于使用探针系统测试被测设备(DUT)的公开的系统和方法,以在低于探针系统周围环境环境露点的温度下测试DUT。 探测系统包括被配置为隔离冷却干燥测试环境的测量室和被配置为选择性地隔离测量室的内部体积的测量室门。 当在低温下测试被包括在基底上的DUT时,选择系统和方法以将至少部分与测量室隔离的干燥环境中的衬底加热至至少高于 露点和/或周围环境的霜点。

    Probe systems and methods
    27.
    发明授权

    公开(公告)号:US10459006B2

    公开(公告)日:2019-10-29

    申请号:US15708681

    申请日:2017-09-19

    Abstract: Probe systems and methods are disclosed herein. The methods include directly measuring a distance between a first manipulated assembly and a second manipulated assembly, contacting first and second probes with first and second contact locations, providing a test signal to an electrical structure, and receiving a resultant signal from the electrical structure. The methods further include characterizing at least one of a probe system and the electrical structure based upon the distance. In one embodiment, the probe systems include a measurement device configured to directly measure a distance between a first manipulated assembly and a second manipulated assembly. In another embodiment, the probe systems include a probe head assembly including a platen, a manipulator operatively attached to the platen, a vector network analyzer (VNA) extender operatively attached to the manipulator, and a probe operatively attached to the VNA extender.

    High voltage chuck for a probe station

    公开(公告)号:US10062597B2

    公开(公告)日:2018-08-28

    申请号:US15670364

    申请日:2017-08-07

    Abstract: A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface.

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