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    Conditioning Circuit that Spectrally Shapes a Serviced Bit Stream
    23.
    发明申请
    Conditioning Circuit that Spectrally Shapes a Serviced Bit Stream 失效
    频谱形成服务位流的调理电路

    公开(公告)号：US20090190649A1

    公开(公告)日：2009-07-30

    申请号：US12419100

    申请日：2009-04-06

    Applicant: Davide Tonietto ,  Ali Ghiasi

    Inventor： Davide Tonietto ,  Ali Ghiasi

    IPC: H03K5/159

    CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

    Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface module includes a line side interface, a board side interface, and a signal conditioning circuit. The line side interface includes a media coupler that receives the line side media, such as copper media or optical media. The board side interface couples the high-speed serial bit stream interface module to the PCB. A signal conditioning circuit communicatively couples to the line side interface and to the board side interface. The signal conditioning circuit receives an RX signal from the line side interface, conditions the RX signal, and provides the RX signal to the board side interface. The signal conditioning circuit receives a TX signal from the board side interface, conditions the TX signal, and provides the TX signal to the board side interface.

    Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速位流接口模块包括线路侧接口，电路板侧接口和信号调理电路。 线路侧接口包括接收线路侧介质的介质耦合器，例如铜介质或光学介质。 板侧接口将高速串行比特流接口模块耦合到PCB。 信号调理电路通信耦合到线路侧接口和电路板侧接口。 信号调理电路从线路侧接口接收RX信号，对RX信号进行调节，并将接收信号提供给电路板侧接口。 信号调理电路从电路板侧接口接收TX信号，调整TX信号，并向板侧接口提供TX信号。

    Conditioning circuit that spectrally shapes a serviced bit stream
    24.
    发明授权
    Conditioning circuit that spectrally shapes a serviced bit stream 失效
    调节电路，使频谱成形服务位流

    公开(公告)号：US07515629B2

    公开(公告)日：2009-04-07

    申请号：US10390495

    申请日：2003-03-17

    Applicant: Davide Tonietto ,  Ali Ghiasi

    Inventor： Davide Tonietto ,  Ali Ghiasi

    IPC: H04B1/38 ,  H04L5/16

    CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

    Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface module includes a line side interface, a board side interface, and a signal conditioning circuit. The line side interface includes a media coupler that receives the line side media, either copper media or optical media. The board side interface couples the high-speed serial bit stream interface module to the PCB. A signal conditioning circuit communicatively couples to the line side interface and to the board side interface. The signal conditioning circuit receives an RX signal from the line side interface, conditions the RX signal, and provides the RX signal to the board side interface. The signal conditioning circuit receives a TX signal from the board side interface, conditions the TX signal, and provides the TX signal to the board side interface.

    Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速位流接口模块包括线路侧接口，电路板侧接口和信号调理电路。 线路侧接口包括接收线路侧介质（铜介质或光介质）的介质耦合器。 板侧接口将高速串行比特流接口模块耦合到PCB。 信号调理电路通信耦合到线路侧接口和电路板侧接口。 信号调理电路从线路侧接口接收RX信号，对RX信号进行调节，并将接收信号提供给电路板侧接口。 信号调理电路从电路板侧接口接收TX信号，调节TX信号，并向板侧接口提供TX信号。

    SYSTEM AND METHOD FOR PROGRAMMABLY ADJUSTING GAIN AND FREQUENCY RESPONSE IN A 10-GIGABIT ETHERNET/FIBRE CHANNEL SYSTEM
    25.
    发明申请
    SYSTEM AND METHOD FOR PROGRAMMABLY ADJUSTING GAIN AND FREQUENCY RESPONSE IN A 10-GIGABIT ETHERNET/FIBRE CHANNEL SYSTEM 有权
    在10-GIGABIT以太网/光纤通道系统中编程调节增益和频率响应的系统和方法

    公开(公告)号：US20070182489A1

    公开(公告)日：2007-08-09

    申请号：US11695405

    申请日：2007-04-02

    Applicant: Ichiro Fujimori ,  Davide Tonietto

    Inventor： Ichiro Fujimori ,  Davide Tonietto

    IPC: H03G3/00

    CPC classification number: H04B10/291

    Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider (704) may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster (702) coupled to the signal divider (704) may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device (130). An equalizer (706) coupled to the signal divider (704) may be configured to equalize the equalization adjustment signal within the multimode PHY device (130). A summer (708) coupled to the equalizer (706) and signal adjuster (702) may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device (130) to create an output equalized signal (712) having a desired gain and/or frequency response.

    Abstract translation: 本发明的各方面可以提供用于调整多模PHY设备的输入信号的增益和/或频率响应的方法和系统。 信号分配器（704）可以在接收到输入信号时将输入信号分配成增益调整信号和/或均衡调整信号。 耦合到信号分配器（704）的信号调节器（702）可以调整多模PHY设备（130）内的分配增益调整信号的增益。 耦合到信号分配器（704）的均衡器（706）可以被配置为均衡多模PHY设备（130）内的均衡调整信号。 耦合到均衡器（706）和信号调节器（702）的加法器（708）可以适于将经调整的调整信号和多模PHY装置（130）内的均衡均衡调整信号相加，以产生输出均衡信号（712） 具有期望的增益和/或频率响应。

    Circuit and method for self trimming frequency acquisition
    27.
    发明授权
    Circuit and method for self trimming frequency acquisition 失效
    自调整频率采集电路及方法

    公开(公告)号：US06807225B1

    公开(公告)日：2004-10-19

    申请号：US09584598

    申请日：2000-05-31

    Applicant: Davide Tonietto ,  Andre M. Bischof

    Inventor： Davide Tonietto ,  Andre M. Bischof

    IPC: H04B138

    CPC classification number: H03L7/087 ,  H03L7/10 ,  H03L2207/06 ,  H04L7/0004 ,  H04L7/033

    Abstract: A circuit and method is disclosed for self trimming in frequency acquisition and clock recovery. The circuit can be simplified as having a VCO in communication with three loops including a trimming loop, a frequency loop and a phase loop. The trimming loop includes a ramp generator for supplying a steady increase of bias current to the VCO causing the frequency of the VCO to increase. At each step, the averaged output of the frequency detector is measured by a comparator. A decision circuit included in the trimming loop registers the output of the comparator in digital format. The trimming loop continues until the decision circuit detects a long string of positives followed by a long string of negatives and at this point, the trimming loop is shut off and the frequency loop is in operation. The frequency loop drives the VCO frequency to within a small difference of the incoming data frequency. The phase loop cleans up the data and locks the phase.

    Abstract translation: 公开了用于频率采集和时钟恢复中的自整定的电路和方法。 该电路可以简化为具有与三个环路通信的VCO，包括修整环路，频率环路和相位环路。 修整回路包括斜坡发生器，用于向VCO提供稳定增加的偏置电流，从而使VCO的频率增加。 在每个步骤中，频率检测器的平均输出由比较器测量。 包括在微调循环中的判定电路以数字格式注册比较器的输出。 修整循环继续，直到判定电路检测到长串正序，然后是长串负片，此时，修整环路被关闭，并且频率环路正在运行。 频率环路将VCO频率驱动到输入数据频率的小差异之内。 相位循环清理数据并锁定相位。

    FEC DRIVEN LINK OPTIMIZATION
    28.
    发明申请
    FEC DRIVEN LINK OPTIMIZATION 审中-公开

    公开(公告)号：US20190028236A1

    公开(公告)日：2019-01-24

    申请号：US15656888

    申请日：2017-07-21

    Applicant: DAVIDE TONIETTO ,  MARC-ANDRE LACROIX ,  HENRY WONG

    Inventor： DAVIDE TONIETTO ,  MARC-ANDRE LACROIX ,  HENRY WONG

    IPC: H04L1/00 ,  H04L12/26

    Abstract: Methods, systems and computer-readable media for optimizing SerDes system parameters based on a bit error rate detected by a forward error correction unit (FEC). A SerDes receiver receives a data stream over a link and uses a FEC to detect error information in the received data stream. The system tunes and optimizes one or more SerDes system parameters using the detected error information. The system minimizes power consumption by decreasing power supply voltage until a maximum acceptable input error rate threshold is reached. The FEC allows the system to tolerate errors in the input data stream up to the threshold while preventing propagation of these errors in the FEC output data stream.

    Bit stream linear equalizer with AGC loop
    30.
    发明授权
    Bit stream linear equalizer with AGC loop 失效
    带AGC循环的位流线性均衡器

    公开(公告)号：US07664170B2

    公开(公告)日：2010-02-16

    申请号：US10417990

    申请日：2003-04-17

    Applicant: Davide Tonietto ,  Ali Ghiasi

    Inventor： Davide Tonietto ,  Ali Ghiasi

    IPC: H03H7/30

    CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  H04J3/04 ,  H04L1/205 ,  H04L25/03343 ,  H04L25/03885

    Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit includes an AGC loop, an equalizer, and an equalizer feedback loop. The AGC loop includes a gain path and a feedback path that couples to the output of the equalizer. The equalizer feedback loop couples to the output of the equalizer and produces spectral shaping control settings that the equalizer uses to produce an equalized high-speed serial bit stream at an equalizer output.

    Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路包括AGC环路，均衡器和均衡器反馈环路。 AGC环路包括增益路径和耦合到均衡器的输出的反馈路径。 均衡器反馈环路耦合到均衡器的输出，并产生频谱整形控制设置，均衡器用于在均衡器输出端产生均衡的高速串行比特流。

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