公开(公告)号：US09087913B2

公开(公告)日：2015-07-21

申请号：US13790004

申请日：2013-03-08

申请人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

发明人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/51

CPC分类号： H01L21/82 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

摘要翻译： 在NVM区域的控制栅极上形成热生长含氧层，在逻辑区域形成高k电介质层和阻挡层。 在含氧层和阻挡层上方形成多晶硅层并进行平坦化。 第一掩模层形成在多晶硅层和控制栅极上，该栅极限定了横向邻近控制栅极的选择栅极位置。 形成定义逻辑门位置的第二掩蔽层。 去除多晶硅层的暴露部分，使得选择栅极保留在选择栅极位置处，并且多晶硅部分保持在逻辑门位置。 在选择和控制栅极和多晶硅部分周围形成介电层。 去除多晶硅部分以在逻辑门位置处产生暴露阻挡层的开口。

公开(公告)号：US08741719B1

公开(公告)日：2014-06-03

申请号：US13790014

申请日：2013-03-08

申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

IPC分类号： H01L21/8247

CPC分类号： H01L27/11534 ,  H01L27/11524 ,  H01L29/66545

摘要： A thermally-grown oxygen-containing gate dielectric and select gate are formed in an NVM region. A high-k gate dielectric, barrier layer, and dummy gate are formed in a logic region. The barrier layer may include a work-function-setting material. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, resulting in an opening. A gate layer is formed over the charge storage layer in the NVM region and within the opening in the logic region, wherein the gate layer within the opening together with the barrier layer form a logic gate in the logic region, and the gate layer is patterned to form a control gate in the NVM region.

摘要翻译： 在NVM区域中形成热生长含氧栅极电介质和选择栅极。 在逻辑区域中形成高k栅极电介质，势垒层和伪栅极。 阻挡层可以包括工作功能设定材料。 第一电介质层形成在NVM和围绕选择栅极和虚拟栅极的逻辑区域中。 从NVM区域去除第一介质层并在逻辑区域中保护。 在选择栅极上形成电荷存储层。 去除虚拟门，导致开口。 栅极层形成在NVM区域中的电荷存储层中并且在逻辑区域的开口内，其中开口内的栅极层与势垒层一起在逻辑区域中形成逻辑门，栅极层被图案化 以在NVM区域中形成控制门。

公开(公告)号：US20130320285A1

公开(公告)日：2013-12-05

申请号：US13486690

申请日：2012-06-01

申请人： Feng Zhou ,  Frank K. Baker, JR. ,  Ko-Min Chang ,  Cheong Min Hong

发明人： Feng Zhou ,  Frank K. Baker, JR. ,  Ko-Min Chang ,  Cheong Min Hong

IPC分类号： H01L45/00

CPC分类号： H01L45/16 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1675

摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

摘要翻译： 一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。 电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。 电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇（911,1211） 。

公开(公告)号：US20130267074A1

公开(公告)日：2013-10-10

申请号：US13790004

申请日：2013-03-08

申请人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, JR.

发明人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, JR.

IPC分类号： H01L21/82 ,  H01L21/28

CPC分类号： H01L21/82 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

摘要翻译： 在NVM区域的控制栅极上形成热生长含氧层，在逻辑区域形成高k电介质层和阻挡层。 在含氧层和阻挡层上方形成多晶硅层并进行平坦化。 第一掩模层形成在多晶硅层和控制栅极上，该栅极限定了横向邻近控制栅极的选择栅极位置。 形成定义逻辑门位置的第二掩蔽层。 去除多晶硅层的暴露部分，使得选择栅极保留在选择栅极位置处，并且多晶硅部分保持在逻辑门位置。 在选择和控制栅极和多晶硅部分周围形成介电层。 去除多晶硅部分以在逻辑门位置处产生暴露阻挡层的开口。

公开(公告)号：US08524557B1

公开(公告)日：2013-09-03

申请号：US13789971

申请日：2013-03-08

申请人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

发明人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

IPC分类号： H01L21/8246

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42348

摘要： A control gate overlying a charge storage layer is formed. A thermally-grown oxygen-containing layer is formed over the control gate. A polysilicon layer is formed over the oxygen-containing layer and planarized. A first masking layer is formed defining a select gate location laterally adjacent the control gate and a second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening in the dielectric. A high-k gate dielectric and logic gate are formed in the opening.

摘要翻译： 形成覆盖电荷存储层的控制栅极。 在控制栅上形成热生长含氧层。 在含氧层上方形成多晶硅层并进行平坦化。 形成第一掩模层，其限定了横向邻近控制栅极的选择栅极位置，并且形成限定逻辑门位置的第二掩模层。 去除多晶硅层的暴露部分，使得选择栅极保留在选择栅极位置处，并且多晶硅部分保持在逻辑门位置。 在选择和控制栅极和多晶硅部分周围形成介电层。 去除多晶硅部分以导致电介质中的开口。 在开口中形成高k栅介质和逻辑门。

公开(公告)号：US20110271035A1

公开(公告)日：2011-11-03

申请号：US12769795

申请日：2010-04-29

申请人： Ross S. Scouller ,  Frank K. Baker, JR. ,  Venkatagiri Chandrasekaran

发明人： Ross S. Scouller ,  Frank K. Baker, JR. ,  Venkatagiri Chandrasekaran

IPC分类号： G06F12/02 ,  G06F9/455 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/401 ,  G06F2212/7203

摘要： A system has an emulation memory having a plurality of sectors for storing information. A controller calculates a number of addresses used divided by a number of valid records in a predetermined address range of the emulation memory. An amount of remaining addresses in a currently used space of the emulation memory which have not been used to store information is calculated. A determination is made whether the calculation is greater than a first predetermined number and whether the amount of remaining addresses is greater than a second predetermined number. If both the fraction is greater than the first predetermined number and the amount of remaining addresses is greater than the second predetermined number, any subsequent update requests are responded to using the currently used space of the emulation memory. Otherwise a compression of the emulation memory is required by copying valid data to an available sector.

摘要翻译： 系统具有具有用于存储信息的多个扇区的仿真存储器。 控制器计算所使用的地址数量除以仿真存储器的预定地址范围中的有效记录数。 计算未被用于存储信息的仿真存储器的当前使用空间中的剩余地址的量。 确定计算是否大于第一预定数量，以及剩余地址的数量是否大于第二预定数量。 如果分数都大于第一预定数量，并且剩余地址的量大于第二预定数量，则使用当前使用的仿真存储器的空间来响应任何后续的更新请求。 否则，通过将有效数据复制到可用扇区，需要对仿真存储器进行压缩。

公开(公告)号：US06898129B2

公开(公告)日：2005-05-24

申请号：US10280294

申请日：2002-10-25

申请人： Craig T. Swift ,  Frank K. Baker, Jr. ,  Erwin J. Prinz ,  Paul A. Ingersoll

发明人： Craig T. Swift ,  Frank K. Baker, Jr. ,  Erwin J. Prinz ,  Paul A. Ingersoll

IPC分类号： G11C16/04 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C16/0466

摘要： A non volatile memory includes a plurality of transistors having a non conductive storage medium. The transistors are erased by injecting holes into the storage medium from both the source edge region and drain edge region of the transistor. In one example, the storage medium is made from silicon nitride isolated from the underlying substrate and overlying gate by silicon dioxide. The injection of holes in the storage medium generates two hole distributions having overlapping portions. The combined distribution of the overlapping portions is above at least a level of the highest concentration of program charge in the overlap region of the storage medium. In one example, the transistors are programmed by hot carrier injection. In some examples, the sources of groups of transistors of the memory are decoded.

摘要翻译： 非易失性存储器包括具有非导电存储介质的多个晶体管。 晶体管通过从晶体管的源极边缘区域和漏极边缘区域两端向存储介质注入空穴而被擦除。 在一个示例中，存储介质由从下面的衬底隔离并由二氧化硅覆盖的栅极制成。 在存储介质中注入孔产生具有重叠部分的两个孔分布。 重叠部分的组合分布高于存储介质的重叠区域中程序电荷的最高浓度的至少一个水平。 在一个示例中，通过热载流子注入对晶体管进行编程。 在一些示例中，解码存储器的晶体管组的源。

公开(公告)号：US06751125B2

公开(公告)日：2004-06-15

申请号：US10287328

申请日：2002-11-04

申请人： Erwin J. Prinz ,  Craig T. Swift ,  Jane A. Yater ,  Sung-Wei Lin ,  Frank K. Baker, Jr.

发明人： Erwin J. Prinz ,  Craig T. Swift ,  Jane A. Yater ,  Sung-Wei Lin ,  Frank K. Baker, Jr.

IPC分类号： G11C1604

CPC分类号： G11C16/3427 ,  G11C16/26 ,  G11C16/3418

摘要： A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current. Accordingly, the voltage thresholds of transistors having an erased state can be reduced, wherein the read gate voltage can be reduced as well.

摘要翻译： 一种用于降低存储器阵列中的读栅极电压的技术，包括具有用于存储指示存储在单元中的值的电荷的晶体管的存储单元。 在一个示例中，大于衬底电压的电压被施加到阵列的存储器单元的晶体管的源极，以增加由于体效应引起的晶体管的阈值电压。 读栅极电压大于比基板电压大的源极电压。 小于源极电压的非读取电压被施加到未选择行的晶体管的栅极以减少泄漏电流。 利用本实施例，具有擦除状态的晶体管的阈值电压可以小于0V。 利用一些实施例，由于栅极电压的降低可以降低由栅极电压引起的读取干扰。 在其他示例中，负电压施加到未选择的行的栅极以防止漏电流。 因此，可以减少具有擦除状态的晶体管的电压阈值，其中读取栅极电压也可以减小。

公开(公告)号：US20150318024A1

公开(公告)日：2015-11-05

申请号：US14266168

申请日：2014-04-30

申请人： FRANK K. BAKER, JR.

发明人： FRANK K. BAKER, JR.

IPC分类号： G11C5/06 ,  G11C13/00

CPC分类号： G11C14/009 ,  G11C5/06 ,  G11C13/0069 ,  G11C14/0081

摘要： A memory cell includes a first storage node and a second storage node that is complementary to the first storage node. A first bidirectional resistive memory element (BRME) includes a first terminal, a second BRME includes a first terminal. A first access transistor couples the first storage node to a first bit line. A second access transistor couples the second storage node to a second bit line. A third transistor couples the first terminal of the first BRME to the second bit line. A fourth transistor couples the first terminal of the second BRME to the first bit line.

摘要翻译： 存储单元包括与第一存储节点互补的第一存储节点和第二存储节点。 第一双向电阻存储器元件（BRME）包括第一端子，第二BRME包括第一端子。 第一存取晶体管将第一存储节点耦合到第一位线。 第二存取晶体管将第二存储节点耦合到第二位线。 第三晶体管将第一BRME的第一端子耦合到第二位线。 第四晶体管将第二BRME的第一端耦合到第一位线。

公开(公告)号：US09118008B2

公开(公告)日：2015-08-25

申请号：US14301900

申请日：2014-06-11

申请人： Feng Zhou ,  Frank K. Baker, Jr. ,  Ko-Min Chang ,  Cheong Min Hong

发明人： Feng Zhou ,  Frank K. Baker, Jr. ,  Ko-Min Chang ,  Cheong Min Hong

IPC分类号： H01L21/00 ,  H01L45/00

CPC分类号： H01L45/16 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1675

摘要： A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

摘要翻译： 一种电阻随机存取存储器（ReRAM）单元，包括在第一导电电极上的第一导电电极和介电存储材料层。 电介质存储材料层有利于在将细丝形成电压施加到电池时形成导电细丝。 电池包括位于介电存储材料层上的第二导电电极和包括与电介质存储材料层接触并与第一导电电极或第二导电电极接触的多个纳米团簇的导电纳米团簇（911,1211） 。