公开(公告)号：US20060063346A1

公开(公告)日：2006-03-23

申请号：US11149708

申请日：2005-06-10

Applicant: Jong-Cheol Lee ,  Ki-Vin Im ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Han-Mei Choi ,  Gab-Jin Nam

Inventor： Jong-Cheol Lee ,  Ki-Vin Im ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Han-Mei Choi ,  Gab-Jin Nam

IPC: H01L21/20

CPC classification number: H01L21/0228 ,  C23C16/45531 ,  C23C16/4554 ,  C23C16/45553 ,  C23C16/515 ,  H01L21/02274 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31691 ,  H01L28/40 ,  H01L28/65

Abstract: In a method of forming a layer using an atomic layer deposition process, after a substrate is loaded into a chamber, a reactant is provided onto the substrate to form a preliminary layer. Atoms in the preliminary layer are partially removed from the preliminary layer using plasma formed from an inert gas such as an argon gas, a xenon gas or a krypton gas, or an inactive gas such as an oxygen gas, a nitrogen gas or a nitrous oxide gas to form a desired layer. Processes for forming the desired layer may be simplified. A highly integrated semiconductor device having improved reliability may be economically manufactured so that time and costs required for the manufacturing of the semiconductor device may be reduced.

Abstract translation: 在使用原子层沉积工艺形成层的方法中，在将衬底装载到室中之后，将反应物提供到衬底上以形成预备层。 使用由诸如氩气，氙气或氪气等惰性气体形成的等离子体或氧气，氮气或一氧化二氮等惰性气体，从预备层中部分除去原料中的原子 气体形成所需层。 可以简化用于形成所需层的工艺。 可以经济地制造具有提高的可靠性的高度集成的半导体器件，从而可以减少制造半导体器件所需的时间和成本。

公开(公告)号：US20060060907A1

公开(公告)日：2006-03-23

申请号：US11273505

申请日：2005-11-14

Applicant: Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

Inventor： Ki-Chul Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  Sung-Tae Kim ,  Thomas Kwon ,  Han-Mei Choi ,  Jae-Soon Lim

IPC: H01L27/108

CPC classification number: H01L21/32051 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

Abstract: A conductive contact plug extends through an opening in the dielectric layer to contact the substrate and includes a widened pad portion extending onto the dielectric layer adjacent the opening. An ohmic pattern is disposed on the pad portion of the plug, and a barrier pattern is disposed on the ohmic pattern. A concave first capacitor electrode is disposed on the barrier pattern and defines a cavity opening away from the substrate. A capacitor dielectric layer conforms to a surface of the first capacitor electrode and a second capacitor electrode is disposed on the capacitor dielectric layer opposite the first capacitor electrode. Sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug may be substantially coplanar, and the device may further include an etch stopper layer conforming to at least sidewalls of the ohmic pattern, the barrier pattern and the pad portion of the contact plug. Related fabrication methods are described.

Abstract translation: 导电接触插塞延伸穿过电介质层中的开口以接触衬底并且包括延伸到邻近开口的电介质层上的加宽焊盘部分。 欧姆图案设置在插头的焊盘部分上，并且阻挡图案设置在欧姆图案上。 凹陷的第一电容器电极设置在阻挡图案上并且限定了远离基板的空腔。 电容器电介质层符合第一电容器电极的表面，并且第二电容器电极设置在与第一电容器电极相对的电容器电介质层上。 欧姆图案的侧壁，接触塞的阻挡图案和焊盘部分可以是基本上共面的，并且该器件还可以包括符合至少欧姆图案的侧壁，阻挡图案和焊盘部分的蚀刻停止层 接触插头。 描述相关的制造方法。

公开(公告)号：US20050081787A1

公开(公告)日：2005-04-21

申请号：US10951937

申请日：2004-09-28

Applicant: Ki-Vin Im ,  Sung-Tae Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  In-Sung Park ,  Eun-Ae Chung ,  Ki-Yeon Park ,  Seung-Hwan Lee

Inventor： Ki-Vin Im ,  Sung-Tae Kim ,  Young-Sun Kim ,  Gab-Jin Nam ,  In-Sung Park ,  Eun-Ae Chung ,  Ki-Yeon Park ,  Seung-Hwan Lee

IPC: H01L21/205 ,  C23C16/44 ,  C23C16/455 ,  C23C16/00

CPC classification number: C23C16/45544

Abstract: Methods of supplying a source to a reactor include charging a gaseous source into a charging volume by selectively activating a source charger coupled between the charging volume and a source reservoir. The gaseous source is then supplied from the charging volume into a deposition process reactor by selectively activating a source supplier coupled between the charging volume and the reactor after the gaseous source in the charging volume attains a desired internal pressure. Apparatus for supplying a source and methods and apparatus for depositing an atomic layer are also provided.

Abstract translation: 向反应器供应源的方法包括通过选择性地启动耦合在充电容积和源储存器之间的源极充电器将气态源充电到充电容积中。 然后，在充电容积中的气体源达到期望的内部压力之后，通过选择性地启动耦合在充电容积和反应器之间的源供应器，将气态源从充电容积供应到沉积工艺反应器中。 还提供了用于提供源的装置和用于沉积原子层的方法和装置。

公开(公告)号：US09153696B2

公开(公告)日：2015-10-06

申请号：US14192074

申请日：2014-02-27

Applicant: Tae-Hyun An ,  Toshiro Nakanishi ,  Gab-Jin Nam ,  Jong-Ho Lee

Inventor： Tae-Hyun An ,  Toshiro Nakanishi ,  Gab-Jin Nam ,  Jong-Ho Lee

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7856 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

Abstract translation: 半导体器件包括：衬底，其包括NMOS区，在NMOS区中从衬底突出的鳍有源区，鳍有源区包括上表面和侧壁;栅极电介质层，位于鳍的上表面和侧壁上 有源区，栅极电介质层上的第一金属栅电极，第一金属栅电极在翅片有源区的上表面具有第一厚度，在鳍有源区的侧壁具有第二厚度，第二金属栅电极 所述第二金属栅电极在所述翅片有源区的上表面具有第三厚度，在所述鳍有源区的所述侧壁处具有第四厚度，其中所述第三厚度小于所述第四厚度。

公开(公告)号：US20120100684A1

公开(公告)日：2012-04-26

申请号：US13280430

申请日：2011-10-25

Applicant: Ji-Young Min ,  Yu-Gyun Shin ,  Gab-Jin Nam ,  Young-Pil Kim

Inventor： Ji-Young Min ,  Yu-Gyun Shin ,  Gab-Jin Nam ,  Young-Pil Kim

IPC: H01L21/336 ,  B82Y40/00

CPC classification number: H01L29/66545 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/165 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed.

Abstract translation: 制造半导体器件的方法包括在衬底上顺序地形成第一栅极绝缘层和第二栅极绝缘层，将杂质离子注入到衬底中并执行用于激活杂质离子以形成源极和漏极区域的第一热处理， 以及在第一热处理完成之后在衬底上形成第三栅极绝缘层。

公开(公告)号：US07696563B2

公开(公告)日：2010-04-13

申请号：US11896834

申请日：2007-09-06

Applicant: Sug-Hun Hong ,  Myoung-Bum Lee ,  Gab-Jin Nam

Inventor： Sug-Hun Hong ,  Myoung-Bum Lee ,  Gab-Jin Nam

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L29/66833 ,  H01L29/7923

Abstract: A non-volatile memory device includes a tunnel insulating layer pattern on a channel region of a substrate, a charge trapping layer pattern on the tunnel insulating layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode including a conductive layer pattern on the blocking layer pattern and a barrier layer pattern on the conductive layer pattern. The conductive layer pattern includes a metal.

Abstract translation: 非易失性存储器件包括在衬底的通道区域上的隧道绝缘层图案，隧道绝缘层图案上的电荷俘获层图案，电荷俘获层图案上的阻挡层图案，以及包括导电 阻挡层图案上的层图案和导电层图案上的阻挡层图案。 导电层图案包括金属。

公开(公告)号：US07396719B2

公开(公告)日：2008-07-08

申请号：US10873256

申请日：2004-06-23

Applicant: Kyoung-seok Kim ,  Hong-bae Park ,  Bong-hyun Kim ,  Sung-tae Kim ,  Jong-wan Kwon ,  Jung-hyun Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Gab-jin Nam ,  Young-sun Kim

Inventor： Kyoung-seok Kim ,  Hong-bae Park ,  Bong-hyun Kim ,  Sung-tae Kim ,  Jong-wan Kwon ,  Jung-hyun Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Gab-jin Nam ,  Young-sun Kim

IPC: H01L21/471

CPC classification number: H01L21/0228 ,  C23C16/308 ,  C23C16/45531 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02181 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3143 ,  H01L21/31645

Abstract: A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.

Abstract translation: 使用原子层沉积（ALD）形成高电介质膜的方法以及制造具有高电介质膜的电容器的方法包括将含有金属元素的前体供应到半导体衬底并清洗反应器; 供应氧化剂并清洗反应器; 并供应含氮的反应源并清洗反应器。

公开(公告)号：US07135422B2

公开(公告)日：2006-11-14

申请号：US10884507

申请日：2004-07-02

Applicant: Gab-Jin Nam ,  Jong-Wan Kwon ,  Han-Mei Choi ,  Jae-Soon Lim ,  Seung-Hwan Lee ,  Ki-Chul Kim ,  Sung-Tae Kim ,  Young-Sun Kim

Inventor： Gab-Jin Nam ,  Jong-Wan Kwon ,  Han-Mei Choi ,  Jae-Soon Lim ,  Seung-Hwan Lee ,  Ki-Chul Kim ,  Sung-Tae Kim ,  Young-Sun Kim

IPC: H01L21/31

CPC classification number: H01L21/0228 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45529 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31645 ,  H01L28/40 ,  H01L28/90

Abstract: Multi-layered structures formed using atomic-layer deposition processes include multiple metal oxide layers wherein the metal oxide layers are formed without the presence of interlayer oxide layers and may include different metal oxide compositions.

Abstract translation: 使用原子层沉积工艺形成的多层结构包括多个金属氧化物层，其中形成金属氧化物层而不存在层间氧化物层，并且可以包括不同的金属氧化物组合物。

公开(公告)号：US20060166476A1

公开(公告)日：2006-07-27

申请号：US11339416

申请日：2006-01-25

Applicant: Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

Inventor： Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

IPC: H01L21/471

CPC classification number: H01L21/022 ,  C23C14/5826 ,  C23C14/586 ,  C23C16/56 ,  H01L21/02142 ,  H01L21/02252 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/3143 ,  H01L21/31645 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/115 ,  H01L27/11521 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

Abstract: In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference between the susceptor and a ground, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer including a metal oxynitride doped with silicon having enough content of nitrogen is formed on the first dielectric layer. Therefore, dielectric properties of the dielectric structure comprising the first and the second dielectric layers can be improved and a leakage current can be greatly decreased. By adapting the dielectric structure to a gate insulation layer and/or to a dielectric layer of a capacitor or of a non-volatile semiconductor memory device, capacitances and electrical properties can be improved.

Abstract translation: 在制造电介质结构的方法中，在通过使用掺杂有硅的金属氧化物在基板上形成第一介电层之后，将基板放置在室的基座上。 通过在控制基座和接地之间的电压差的同时用等离子体处理第一电介质层，在第一电介质层上形成第二电介质层。 在第一电介质层上形成包括掺杂有足够的氮含量的硅的金属氮氧化物的第二电介质层。 因此，可以提高包括第一和第二电介质层的电介质结构的介电性能，并且可以大大降低泄漏电流。 通过使电介质结构适应于栅极绝缘层和/或电容器或非易失性半导体存储器件的电介质层，可以提高电容和电性能。

公开(公告)号：US20060138523A1

公开(公告)日：2006-06-29

申请号：US11311143

申请日：2005-12-20

Applicant: Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

Inventor： Jong-Cheol Lee ,  Jae-Hyoung Choi ,  Han-Mei Choi ,  Gab-Jin Nam ,  Young-Sun Kim

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

Abstract: Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.

Abstract translation: 本发明的示例实施例公开了一种非易失性半导体存储器件，其可以包括具有增强介电常数的介电层。 可以在衬底上依次形成隧道氧化物层图案和浮栅。 可以使用脉冲激光沉积工艺在浮栅上形成包括掺杂有III族过渡金属的金属氧化物的电介质层图案。 具有增加的介电常数的电介质层图案可以由掺杂有过渡金属如钪，钇或镧的金属氧化物形成。