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    SEMICONDUCTOR DEVICES INCLUDING A VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME
    21.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING A VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME 有权
    包括垂直通道晶体管的半导体器件及其制造方法

    公开(公告)号：US20130043525A1

    公开(公告)日：2013-02-21

    申请号：US13588513

    申请日：2012-08-17

    申请人： Hak-soo YU ,  Chulwoo PARK ,  Hyun-Woo CHUNG ,  Sua KIM ,  Hyunho CHOI ,  Hongsun HWANG

    发明人： Hak-soo YU ,  Chulwoo PARK ,  Hyun-Woo CHUNG ,  Sua KIM ,  Hyunho CHOI ,  Hongsun HWANG

    IPC分类号： H01L29/78

    CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

    摘要： According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.

    摘要翻译： 根据示例性实施例，半导体器件包括从衬底突出的多个有源柱。 每个有源支柱包括上和下掺杂区之间的沟道区。 接触栅电极面对沟道区并连接到字线。 字线在第一方向延伸。 位线连接到下掺杂区域并沿第二方向延伸。 该半导体器件还包括连接多个有源支柱的至少两个相邻有效支柱的沟道区域的串体连接部分。

    MEMORY DEVICE FOR MANAGING TIMING PARAMETERS
    22.
    发明申请
    MEMORY DEVICE FOR MANAGING TIMING PARAMETERS 有权
    用于管理时序参数的存储器件

    公开(公告)号：US20130039135A1

    公开(公告)日：2013-02-14

    申请号：US13569636

    申请日：2012-08-08

    申请人： Uk-song KANG ,  Chul-woo PARK ,  Hak-soo YU ,  Hong-sun HWANG

    发明人： Uk-song KANG ,  Chul-woo PARK ,  Hak-soo YU ,  Hong-sun HWANG

    IPC分类号： G11C7/22

    CPC分类号： G11C11/4076 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/4093

    摘要： A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

    摘要翻译： 执行在包括多个存储体的存储器件中执行写入操作的方法。 每个银行包括至少包括第一子银行和第二子银行的两个或多个子行。 该方法包括：执行第一行周期以写入第一子行的第一字线，第一行周期包括多个第一子周期，用于执行特定动作的每个子周期; 以及执行第二行周期以写入所述第二子行的第一字线，所述第二行周期包括与所述多个第一子周期相同类型的多个第二子周期。 第一行周期与第二行周期重叠，第一子周期的第一类型子周期与第二子周期的第二类型子周期重叠，第一类型和第二类型是不同类型。

    MEMORY DEVICE, COMPUTER SYSTEM INCLUDING THE SAME, AND OPERATING METHODS THEREOF
    23.
    发明申请
    MEMORY DEVICE, COMPUTER SYSTEM INCLUDING THE SAME, AND OPERATING METHODS THEREOF 有权
    存储器件，包括其的计算机系统及其操作方法

    公开(公告)号：US20120260060A1

    公开(公告)日：2012-10-11

    申请号：US13437418

    申请日：2012-04-02

    申请人： JOO YOUNG HWANG ,  Hak Soo Yu

    发明人： JOO YOUNG HWANG ,  Hak Soo Yu

    IPC分类号： G06F12/08

    CPC分类号： G06F17/30156 ,  G06F12/0238 ,  G06F12/1018 ,  G06F2212/7201

    摘要： A memory device includes a hash table storing a hash value, a bit value, and a page address for each of a plurality of pages, a memory cell unit configured to store the pages and output contents corresponding to the page addresses of the pages having a same hash value, and a controller including a comparator configured to compare the contents output from the memory cell unit and change at least one bit value associated with a respective one of the pages upon determining that the contents of the pages are the same.

    摘要翻译： 存储装置包括存储多页的散列值，位值和页面地址的哈希表，存储单元单元，被配置为存储页面，并且输出与具有页面的页面的页面地址对应的内容 以及包括比较器的控制器，所述比较器被配置为在确定所述页面的内容相同时比较从所述存储器单元单元输出的内容并改变与所述页面中的相应页面相关联的至少一个位值。

    Semiconductor Memory Devices
    24.
    发明申请
    Semiconductor Memory Devices 有权
    半导体存储器件

    公开(公告)号：US20110305059A1

    公开(公告)日：2011-12-15

    申请号：US13153749

    申请日：2011-06-06

    申请人： Hak-soo Yu ,  Hong-sun Hwang ,  Kwan-young Oh ,  In-gyu Baek ,  Jin-hyoung Kwon

    发明人： Hak-soo Yu ,  Hong-sun Hwang ,  Kwan-young Oh ,  In-gyu Baek ,  Jin-hyoung Kwon

    IPC分类号： G11C5/06 ,  G11C7/00

    CPC分类号： G11C5/063

    摘要： Semiconductor memory devices include a first storage layer and a second storage layer, each of which includes at least one array, and a control layer for controlling access to the first storage layer and the second storage layer so as to write data to or read data from the array included in the first storage layer or the second storage layer in correspondence to a control signal. A memory capacity of the array included in the first storage layer is different from a memory capacity of the array included in the second storage layer.

    摘要翻译： 半导体存储器件包括第一存储层和第二存储层，每个存储层包括至少一个阵列，以及用于控制对第一存储层和第二存储层的访问的控制层，以便将数据写入或从 该阵列包括在与控制信号对应的第一存储层或第二存储层中。 包括在第一存储层中的阵列的存储器容量不同于包括在第二存储层中的阵列的存储器容量。

    Data line layout and line driving method in semiconductor memory device
    25.
    发明授权
    Data line layout and line driving method in semiconductor memory device 有权
    半导体存储器件中的数据线布局和线驱动方法

    公开(公告)号：US07697314B2

    公开(公告)日：2010-04-13

    申请号：US12006502

    申请日：2008-01-03

    申请人： Nam-Seog Kim ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18 ,  G11C11/417

    摘要： A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.

    摘要翻译： 数据线布局结构包括多个第一数据线，第二数据线，第三数据线，第一数据线驱动器和第二数据线驱动器。 多个第一数据线连接到存储器垫中的子垫，使得预定数量的第一数据线连接到每个子垫。 第二数据线的布置量比第一数据线的数量少，从而形成相对于第一数据线的层次。 第三数据线被布置成相对于第二数据线形成层级，并且将通过第二数据线提供的数据传送到数据锁存器。 第一数据线驱动器连接在第一数据线和第二数据线之间，并且执行用于输出第一数据线的逻辑“或”运算，以驱动对应的第二数据线。 第二数据线驱动器连接在第二数据线和第三数据线之间，并且执行用于输出第二数据线的逻辑“或”运算，以驱动第三数据线。

    Semiconductor memory device with hierarchical bit line structure
    26.
    发明授权
    Semiconductor memory device with hierarchical bit line structure 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US07656723B2

    公开(公告)日：2010-02-02

    申请号：US12347239

    申请日：2008-12-31

    申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C7/22

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

    Synchronous burst semiconductor memory device with parallel input/output data strobe clocks
    27.
    发明授权
    Synchronous burst semiconductor memory device with parallel input/output data strobe clocks 有权
    具有并行输入/输出数据选通时钟的同步脉冲串半导体存储器件

    公开(公告)号：US06091663A

    公开(公告)日：2000-07-18

    申请号：US137645

    申请日：1998-08-20

    申请人： Su-Chul Kim ,  Hak-Soo Yu ,  Min-Chul Chung

    发明人： Su-Chul Kim ,  Hak-Soo Yu ,  Min-Chul Chung

    IPC分类号： G11C11/407 ,  G06F12/00 ,  G11C7/10 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/1078 ,  G11C7/1051

    摘要： A synchronous burst semiconductor memory device operating in synchronism with at least one external clock signal and capable of accessing data on every edge of the external clock signal is provided. The burst memory device includes a clock generator for generating a number of data output/input strobe clock signals synchronized with the external clock signal in response to a plurality of input information signals, and a data-out/in buffer for outputting/inputting internal/external data in synchronism with the data output/input strobe clock signals.

    摘要翻译： 提供了与至少一个外部时钟信号同步操作且能够访问外部时钟信号的每个边缘上的数据的同步突发半导体存储器件。 突发存储器件包括：时钟发生器，用于响应于多个输入信息信号产生与外部时钟信号同步的多个数据输出/输入选通时钟信号;以及数据输出/输入缓冲器，用于输出/输入内部/ 外部数据与数据输出/输入选通时钟信号同步。

    MEMORY MODULES AND MEMORY SYSTEMS
    29.
    发明申请
    MEMORY MODULES AND MEMORY SYSTEMS 有权
    存储器模块和存储器系统

    公开(公告)号：US20140189215A1

    公开(公告)日：2014-07-03

    申请号：US14083033

    申请日：2013-11-18

    申请人： UK-SONG KANG ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jong-Pil Son

    发明人： UK-SONG KANG ,  Chul-Woo Park ,  Hak-Soo Yu ,  Jong-Pil Son

    IPC分类号： G11C11/406 ,  G06F12/02

    CPC分类号： G11C11/40607 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4087

    摘要： A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.

    摘要翻译： 存储器模块包括多个存储器件和缓冲器芯片。 缓冲芯片管理存储器件。 缓冲芯片包括根据轮胎存储单元行的数据保持时间将存储器件的多个存储单元行分组成多个组的刷新控制电路。 缓冲器芯片有选择地刷新周期性地重复的多个刷新时间区域中的每一个中的多个组中的每一个，并将各个刷新周期分别应用于多个组。

    Memory device for managing timing parameters
    30.
    发明授权
    Memory device for managing timing parameters 有权
    用于管理时序参数的存储器

    公开(公告)号：US08693269B2

    公开(公告)日：2014-04-08

    申请号：US13569636

    申请日：2012-08-08

    申请人： Uk-song Kang ,  Chul-woo Park ,  Hak-soo Yu ,  Hong-sun Hwang

    发明人： Uk-song Kang ,  Chul-woo Park ,  Hak-soo Yu ,  Hong-sun Hwang

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4076 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/4093

    摘要： A method of performing write operations in a memory device including a plurality of bank is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

    摘要翻译： 执行在包括多个存储体的存储器件中执行写入操作的方法。 每个银行包括至少包括第一子银行和第二子银行的两个或多个子行。 该方法包括：执行第一行周期以写入第一子行的第一字线，第一行周期包括多个第一子周期，用于执行特定动作的每个子周期; 以及执行第二行周期以写入所述第二子行的第一字线，所述第二行周期包括与所述多个第一子周期相同类型的多个第二子周期。 第一行周期与第二行周期重叠，第一子周期的第一类型子周期与第二子周期的第二类型子周期重叠，第一类型和第二类型是不同类型。