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    Methods of forming integrated circuit devices having anisotropically-oxidized nitride layers
    22.
    发明授权
    Methods of forming integrated circuit devices having anisotropically-oxidized nitride layers 失效
    形成具有各向异性氧化的氮化物层的集成电路器件的方法

    公开(公告)号：US07989333B2

    公开(公告)日：2011-08-02

    申请号：US12468296

    申请日：2009-05-19

    申请人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    发明人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3105 ,  H01L29/6653

    摘要： Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成栅电极，并在栅电极的侧壁和上表面上形成氮化物层。 然后在使得在栅电极的上表面上延伸的氮化物层的第一部分相对于在栅电极的侧壁上延伸的氮化物层的第二部分被更大程度地氧化的条件下，各向异性地氧化氮化物层。 氮化物层的氧化的第一部分的厚度相对于氮化物层的氧化的第二部分的厚度的比例可以在约3:1至约7:1的范围内。

    Methods for fabricating improved gate dielectrics
    24.
    发明授权
    Methods for fabricating improved gate dielectrics 失效
    制造改进的栅极电介质的方法

    公开(公告)号：US07759263B2

    公开(公告)日：2010-07-20

    申请号：US11806338

    申请日：2007-05-31

    申请人： Woong-Hee Sohn ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Hee-Sook Park ,  Jae-Hwa Park ,  Geum-Jung Seong

    发明人： Woong-Hee Sohn ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Hee-Sook Park ,  Jae-Hwa Park ,  Geum-Jung Seong

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823481 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/2822 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78 ,  Y10S438/981

    摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

    摘要翻译： 公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。 这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。 每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层 。 得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

    Semiconductor integrated circuit device and related method
    25.
    发明授权
    Semiconductor integrated circuit device and related method 有权
    半导体集成电路器件及相关方法

    公开(公告)号：US07718520B2

    公开(公告)日：2010-05-18

    申请号：US11723725

    申请日：2007-03-21

    申请人： Hee-sook Park

    发明人： Hee-sook Park

    IPC分类号： H01L21/00

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L29/66628

    摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.

    摘要翻译： 本发明的实施例提供一种半导体集成电路器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底的单元阵列区域和外围电路区域中形成多个预选栅电极结构; 在电池阵列区域和外围区域中的半导体衬底上形成选择性外延膜; 将杂质注入到至少一些选择性外延膜中以在电池阵列区域和外围电路区域中形成升高的源极/漏极区域; 形成第1层间绝缘膜; 以及图案化所述第一层间绝缘膜以形成暴露所述升高的源极/漏极区域的多个第一开口。 该方法还包括形成第一欧姆膜，第一阻挡膜和金属膜; 以及去除金属膜，第一阻挡膜和第一欧姆膜中的每一个的部分。

    Semiconductor devices including high-k dielectric materials
    26.
    发明授权
    Semiconductor devices including high-k dielectric materials 失效
    包括高k电介质材料的半导体器件

    公开(公告)号：US07696552B2

    公开(公告)日：2010-04-13

    申请号：US11227541

    申请日：2005-09-15

    申请人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Byung-Hak Lee ,  Hee-Sook Park

    发明人： Sun-Pil Youn ,  Chang-Won Lee ,  Woong-Hee Sohn ,  Gil-Heyun Choi ,  Jong-Ryeol Yoo ,  Dong-Chan Lim ,  Jae-Hwa Park ,  Byung-Hak Lee ,  Hee-Sook Park

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/11526 ,  H01L21/82345 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11546

    摘要： A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.

    摘要翻译： 半导体器件包括在半导体衬底上的第一导电层，在第一导电层上包括高k电介质材料的电介质层，在电介质层上掺杂有P型杂质的多晶硅的第二导电层，以及第三导电层 层，其包括在第二导电层上的金属。 在一些器件中，第一栅极结构形成在主单元区域中，并且包括隧道氧化物层，浮置栅极，第一高k电介质层和控制栅极。 控制栅极包括掺杂有P型杂质和金属层的多晶硅层。 第二栅极结构形成在主单元区域的外部，并且包括隧道氧化物层，导电层和金属层。 第三栅极结构形成在周边单元区域中，并且包括具有比导电层窄的宽度的隧道氧化物，导电层和高k电介质层。 还公开了方法实施例。

    Methods of forming gate structures for semiconductor devices
    28.
    发明授权
    Methods of forming gate structures for semiconductor devices 有权
    形成半导体器件栅极结构的方法

    公开(公告)号：US07521316B2

    公开(公告)日：2009-04-21

    申请号：US11221062

    申请日：2005-09-07

    申请人： Woong-Hee Sohn ,  Chang-Won Lee ,  Sun-Pil Youn ,  Gil-Heyun Choi ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Hee-Sook Park

    发明人： Woong-Hee Sohn ,  Chang-Won Lee ,  Sun-Pil Youn ,  Gil-Heyun Choi ,  Byung-Hak Lee ,  Jong-Ryeol Yoo ,  Hee-Sook Park

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28273 ,  H01L29/42324

    摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，形成绝缘衬垫。 更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极 所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。 漏电阻氧化物可以形成在第二栅电极的侧壁上。 绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。 此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。 还讨论了相关结构。

    Semiconductor device and method of fabricating the same
    29.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07518214B2

    公开(公告)日：2009-04-14

    申请号：US11586610

    申请日：2006-10-26

    申请人： Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

    发明人： Dong-chan Lim ,  Byung-hee Kim ,  Tae-ho Cha ,  Hee-sook Park ,  Geum-jung Seong

    IPC分类号： H01L29/00

    CPC分类号： H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4941 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

    摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.

    摘要翻译： 半导体器件的集成电路具有不易发生严重RC延迟的线型图案。 该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物 分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。 集成电路可以构成半导体器件的栅极线。 集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。 蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。