公开(公告)号：US20250096052A1

公开(公告)日：2025-03-20

申请号：US18469674

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Mohamed R. Saber ,  Hanyu Song ,  Fanyi Zhu ,  Bai Nie ,  Srinivas V. Pietambaram ,  Deniz Turan ,  Yonggang Li ,  Naiya Soetan-Dodd ,  Shuren Qu

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: Microelectronic assemblies with glass cores that have undergone localized thermal healing and/or localized doping in regions adjacent to glass surface are disclosed. In one example, a microelectronic assembly includes a glass core having a first face, an opposing second face, a sidewall extending between the first face and the second face, a surface region, and a bulk region, where the surface region is a portion of the glass core that starts at a surface of the first face, the second face, or the sidewall and extends from the surface into the glass core by a total depth of up to about 50 micron, the bulk region is a portion of the glass core further away from the surface than the surface region, and a density of the surface region is higher than a density of the bulk region, e.g., at least about 5% higher or at least about 7.5% higher.

公开(公告)号：US20250093413A1

公开(公告)日：2025-03-20

申请号：US18963838

申请日：2024-11-29

Applicant: Intel Corporation

Inventor： Zhen ZHOU ,  Renzhi LIU ,  Jong-Ru GUO ,  Kenneth P. FOUST ,  Jason A. MIX ,  Kai XIAO ,  Zuoguo WU ,  Daqiao DU

IPC: G01R31/302 ,  G01R31/28 ,  G01R31/303 ,  H01P3/08 ,  H01Q9/16 ,  H04B5/48

Abstract: A high volume manufacturing (HVM) test system including a test device defining an opening configured to receive a package under test, the test device including an external access agent (EAA) including: a first leaky surface wave launcher for near field wireless communication, the first leaky surface wave launcher configured to wirelessly provide sideband signals to and wirelessly receive the sideband signals from a silicon package agent physically positioned in a separate package as the EAA; and a first transceiver electrically coupled to the first leaky surface wave launcher, the first transceiver configured to: process the sideband signals received by the first leaky surface wave launcher; and generate the sideband signals for wireless transmission by the first leaky surface wave launcher.

公开(公告)号：US12255897B2

公开(公告)日：2025-03-18

申请号：US18478692

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Hong C. Li ,  John B. Vicente ,  Prashant Dewan

IPC: H04L9/40 ,  G06F21/51 ,  G06F21/53 ,  H04L67/02

Abstract: Systems and methods may provide for receiving web content and determining a trust level associated with the web content. Additionally, the web content may be mapped to an execution environment based at least in part on the trust level. In one example, the web content is stored to a trust level specific data container.

公开(公告)号：US12255648B2

公开(公告)日：2025-03-18

申请号：US17350577

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

IPC: H03K19/17788 ,  H03K19/17728 ,  H03K19/17792

Abstract: A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

公开(公告)号：US12255158B2

公开(公告)日：2025-03-18

申请号：US16911543

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Neelam Prabhu Gaunkar ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Diego Correas-Serrano ,  Henning Braunisch

IPC: H01L23/66 ,  H01L23/498 ,  H01P3/00 ,  H01P3/08

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US12255137B2

公开(公告)日：2025-03-18

申请号：US18419015

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Rishabh Mehandru

IPC: H01L23/522 ,  H01L21/8234 ,  H01L25/16 ,  H01L29/06

Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

公开(公告)号：US12254341B2

公开(公告)日：2025-03-18

申请号：US18353694

申请日：2023-07-17

Applicant: Intel Corporation

Inventor： Ravi L. Sahita ,  Tin-Cheung Kung ,  Vedvyas Shanbhogue ,  Barry E. Huntley ,  Arie Aharon

IPC: G06F9/455 ,  G06F9/50 ,  H04L9/06

Abstract: Implementations describe a computing system that implements a plurality of virtual machines inside a trust domain (TD), enabled via a secure arbitration mode (SEAM) of the processor. A processor includes one or more registers to store a SEAM range of memory, a TD key identifier of a TD private encryption key. The processor is capable of initializing a trust domain resource manager (TDRM) to manage the TD, and a virtual machine monitor within the TD to manage the plurality of virtual machines therein. The processor is further capable of exclusively associating a plurality of memory pages with the TD, wherein the plurality of memory pages associated with the TD is encrypted with a TD private encryption key inaccessible to the TDRM. The processor is further capable of using the SEAM range of memory, inaccessible to the TDRM, to provide isolation between the TDRM and the plurality of virtual machines.

公开(公告)号：US12253948B2

公开(公告)日：2025-03-18

申请号：US17092803

申请日：2020-11-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Alexander Bachmutsky ,  Zhongyan Lu ,  Thomas Willhalm

IPC: G06F12/08 ,  G06F12/0817

Abstract: Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory. In connection with DM cache operations, such as cache lines evicted from a CPU, logic implemented in hardware determines whether a cache line in a DM cache is to be evicted and implements the software-defined caching policy for the DM cache including associated memory coherency operations.

公开(公告)号：US20250089156A1

公开(公告)日：2025-03-13

申请号：US18367963

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Mohamed R. SABER ,  Manohar KONCHADY ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Hiroki TANAKA ,  Gang DUAN

IPC: H05K1/02 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

Abstract: Embodiments disclosed herein include an apparatus with a glass core and a via. In an embodiment, the apparatus comprises a layer, where the layer is a solid layer of glass. An opening is provided through the layer, and a via is in the opening. The via comprises a first material, where the first material comprises at least one metallic element, and a second material, where the second material comprises carbon.

公开(公告)号：US20250089092A1

公开(公告)日：2025-03-13

申请号：US18796322

申请日：2024-08-07

Applicant: Intel Corporation

Inventor： Laurent CARIOU ,  Thomas J. KENNEY

IPC: H04W74/0816 ,  H04W84/12

Abstract: This disclosure describes systems, methods, and devices related to defer signal that may be for prioritized access as part of a communication protocol. A device may generate a defer signal to be used with a prioritized access for one or more station devices (STAs). The device may include a rate field and a length field in the defer signal. The device may cause to send the defer signal to the one or more STAs. The benefit of the disclosed defer signal is that that legacy devices may understand it and defer for a certain duration because of the defer signal, all while keeping the defer signal as small as possible to save time.