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    Silicon photonics based fiber coupler
    22.
    发明授权
    Silicon photonics based fiber coupler 有权

    公开(公告)号：US10788638B2

    公开(公告)日：2020-09-29

    申请号：US16245076

    申请日：2019-01-10

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan ,  Masaki Kato

    IPC: G02B6/43 ,  G02B6/42 ,  G02B6/122 ,  G02B6/12

    Abstract: A silicon-based edge coupler for coupling a fiber with a waveguide includes a cantilever member being partially suspended with its anchored end coupled to a silicon photonics die in a first part of a silicon substrate and a free end terminated near an edge region separating a second part of the silicon substrate from the first part. The edge coupler further includes a mechanical stopper formed at the edge region with a gap distance ahead of the free end of the cantilever member. Additionally, a V-groove is formed in the second part of the silicon substrate characterized by a top opening and a bottom plane symmetrically connected by two sloped side walls along a fixed Si-crystallography angle. The V-groove is configured to support a fiber with an end facet being pushed against the mechanical stopper and a core center being aligned with the free end of the cantilever member.

    RECONFIGURABLE FEC
    24.
    发明申请
    RECONFIGURABLE FEC 审中-公开

    公开(公告)号：US20200228146A1

    公开(公告)日：2020-07-16

    申请号：US16831626

    申请日：2020-03-26

    Applicant: INPHI CORPORATION

    Inventor： Volodymyr SHVYDUN

    IPC: H03M13/00 ,  H04B10/60 ,  H04L1/00 ,  H03M13/15

    Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

    Impairment compensation techniques for high performance coherent optical transceivers
    25.
    发明授权
    Impairment compensation techniques for high performance coherent optical transceivers 有权

    公开(公告)号：US10715259B1

    公开(公告)日：2020-07-14

    申请号：US16256637

    申请日：2019-01-24

    Applicant: INPHI CORPORATION

    Inventor： Mario Rafael Hueda ,  José L. Correa Lust ,  Damian Alfonso Morero

    IPC: H04B10/61 ,  H04B10/40 ,  H04J14/02

    Abstract: A method and structure for compensation techniques in coherent optical receivers. The present invention provides a coherent optical receiver with an improved 8×8 adaptive MIMO (Multiple Input, Multiple Output) equalizer configured within a digital signal processor (DSP) to compensate the effects of transmitter I/Q skew in subcarrier multiplexing (SCM) schemes. The 8×8 MIMO equalizer can be configured such that each of the 8 outputs is electrically coupled to 3 of 8 inputs, wherein each of the input-output couplings is configured as a filter. The method includes compensating for impairments to the digital conversion of an optical input signal via the 8×8 MIMO equalizer following other signal processing steps, such as chromatic dispersion (CD)/polarization-mode dispersion (PMD) compensation, carrier recovery, timing synchronization, and cycle slip correction.

    PACKAGE STRUCTURE FOR PHOTONIC TRANSCEIVING DEVICE
    27.
    发明申请
    PACKAGE STRUCTURE FOR PHOTONIC TRANSCEIVING DEVICE 审中-公开

    公开(公告)号：US20200183105A1

    公开(公告)日：2020-06-11

    申请号：US16793550

    申请日：2020-02-18

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. NAGARAJAN ,  Peng-Chih LI ,  Masaki KATO

    IPC: G02B6/42 ,  H04B10/516 ,  H04B10/40

    Abstract: A photonic transceiver apparatus in QSFP package. The apparatus includes a case having a base member, two partial side members, and a lid member to provide a spatial volume with an opening at a back end of the base member. Additionally, the apparatus includes a PCB, installed inside the spatial volume over the base member having a pluggable electrical connector at the back end. Further, the apparatus includes multiple optical transmitting devices in mini-transmit-optical-sub-assembly package, each being mounted on a common support structure and having a laser output port in reversed orientation toward the back end. Furthermore, the apparatus includes a silicon photonics chip, including a fiber-to-silicon attachment module, mounted on the PCB and coupled to a modulation driver module and a trans-impedance amplifier module. Moreover, the apparatus includes a pair of optical input/output ports being back connected to the fiber-to-silicon attachment module.

    LIGHT ENGINE BASED ON SILICON PHOTONICS TSV INTERPOSER
    28.
    发明申请
    LIGHT ENGINE BASED ON SILICON PHOTONICS TSV INTERPOSER 审中-公开

    公开(公告)号：US20200152574A1

    公开(公告)日：2020-05-14

    申请号：US16738844

    申请日：2020-01-09

    Applicant: INPHI CORPORATION

    Inventor： Liang DING ,  Radhakrishnan L. NAGARAJAN

    IPC: H01L23/538 ,  H01L25/16 ,  H01L23/00 ,  G02B6/42

    Abstract: A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.

    Method of reducing power dissipation in a clock distribution network for integrated circuit
    30.
    发明授权
    Method of reducing power dissipation in a clock distribution network for integrated circuit 有权

    公开(公告)号：US10606306B2

    公开(公告)日：2020-03-31

    申请号：US16263705

    申请日：2019-01-31

    Applicant: INPHI CORPORATION

    Inventor： Tomas Alexander Dusatko

    IPC: G06F1/10 ,  H01F17/00 ,  H03H7/01 ,  G06F1/32 ,  H03H11/28 ,  H01L23/66 ,  H03H7/09 ,  H03H7/38

    Abstract: A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network. Various implementations are provided, including single-ended, differential, multi-section, multi-output, and point-to-multi-point implementations, each with an optional low-speed mode switch.

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