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公开(公告)号：US20210385560A1
公开(公告)日：2021-12-09
申请号：US16894611
申请日：2020-06-05
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. NAGARAJAN , Liang DING , Mark PATTERSON , Roberto COCCIOLI , Steve ABOAGYE
Abstract: A co-packaged optical-electrical module includes a module substrate with a minimum lateral dimension no greater than 100 mm. The co-packaged optical-electrical module further includes a main die with a processor chip disposed at a central region of the module substrate, the processor chip being configured to operate with a digital-signal processing (DSP) interface for extra-short-reach data interconnect. Additionally, the co-packaged optical-electrical module includes a plurality of chiplet dies disposed densely along a peripheral region of the module substrate. Each chiplet die is configured to be self-packaged light engine on a sub-module substrate with a minimum lateral dimension to allow a maximum number of chiplet dies on the module substrate with a distance of any chiplet die from the main die smaller than 50 mm for extra-short-reach interconnect operation.
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公开(公告)号：US20180275359A1
公开(公告)日：2018-09-27
申请号：US15985584
申请日：2018-05-21
Applicant: Inphi Corporation
Inventor： Liang DING , Radhakrishnan L. NAGARAJAN , Roberto COCCIOLI
CPC classification number: G02B6/428 , G02B6/13 , G02B6/30 , G02B6/4232 , G02B6/424 , G02B6/4245 , G02B6/4283 , G02B6/4295 , G02B2006/12121 , G02B2006/12142 , H01L21/565 , H01L21/76877 , H01L24/11 , H01L24/81 , H01L25/167 , H01L2224/11334 , H01L2224/12105 , H01L2224/13014 , H01L2224/13016 , H01L2224/16146 , H01L2224/16227 , H01L2224/81191 , H01L2924/06 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/1205 , H01L2924/141 , H01L2924/1426 , H01L2924/1433
Abstract: An optical transceiver by hybrid multichip integration. The optical transceiver includes a PCB with a plurality of prefabricated surface bonding sites. A first chip includes a FOWLP package of multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer is disposed on the PCB by respectively bonding a plurality of conductor balls between the dielectric redistribution layer and the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) in the dielectric molding layer. The optical transceiver further includes a second chip configured as a Sipho die comprising photonics devices embedded in a SOI wafer substantially free from any electronics device process. The second chip is stacked over the first chip with multiple conductor bumps being bonded respectively to the soldering material in the multiple TMVs.
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公开(公告)号：US20170254953A1
公开(公告)日：2017-09-07
申请号：US15586179
申请日：2017-05-03
Applicant: INPHI CORPORATION
Inventor： Liang DING , Radhakrishnan L. NAGARAJAN
CPC classification number: G02B6/132 , G02B6/122 , G02B6/125 , G02B6/136 , G02B2006/12061
Abstract: An silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO2 overlying the first plurality of Si waveguides and a second plurality of Si3N4 waveguides formed on the first layer of SiO2. At least one Si3N4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO2 overlying the second plurality of Si3N4 waveguides. The method of accurately controlling the coupling interlayer SiO2 thickness includes a multilayer SiO2/Si3N4/SiO2 hard mask process for SiO2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.
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Patent Agency Ranking
公开(公告)号：US20210385000A1
公开(公告)日：2021-12-09
申请号：US16894597
申请日：2020-06-05
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. NAGARAJAN , Liang DING , Mark PATTERSON , Roberto COCCIOLI
Abstract: An in-packaged multi-channel light engine is packaged for four or more sub-assemblies of optical-electrical sub-modules. Each is assembled with at least four laser chips, one or more driver chip, and one or more trans-impedance amplifier (TIA) chip separately flip-mounted on a silicon photonics interposer and is coupled to an optical interface block and an electrical interface block on a sub-module substrate. The in-packaged multi-channel light engine further includes a first frame fixture holding the four or more sub-assemblies and a second frame fixture configured to hold the first frame fixture with the four or more sub-assemblies. The in-packaged multi-channel light engine further includes an interposer plate inserted between the sub-module substrates and a module substrate and is compressed between a backplate member attached to a bottom side of the module substrate and a top plate member configured as a heatsink with a plurality of fin structures.
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公开(公告)号：US20180136395A1
公开(公告)日：2018-05-17
申请号：US15855655
申请日：2017-12-27
Applicant: INPHI Corporation
Inventor： Liang DING , Radhakrishnan L. NAGARAJAN
CPC classification number: G02B6/132 , G02B6/122 , G02B6/125 , G02B6/136 , G02B2006/12061
Abstract: An silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO2 overlying the first plurality of Si waveguides and a second plurality of Si3N4 waveguides formed on the first layer of SiO2. At least one Si3N4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO2 overlying the second plurality of Si3N4 waveguides. The method of accurately controlling the coupling interlayer SiO2 thickness includes a multilayer SiO2/Si3N4/SiO2 hard mask process for SiO2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.
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公开(公告)号：US20200152574A1
公开(公告)日：2020-05-14
申请号：US16738844
申请日：2020-01-09
Applicant: INPHI CORPORATION
Inventor： Liang DING , Radhakrishnan L. NAGARAJAN
IPC: H01L23/538 , H01L25/16 , H01L23/00 , G02B6/42
Abstract: A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.
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公开(公告)号：US20170261708A1
公开(公告)日：2017-09-14
申请号：US15481994
申请日：2017-04-07
Applicant: INPHI CORPORATION
Inventor： Liang DING , Radhakrishnan L. NAGARAJAN , Roberto COCCIOLI
CPC classification number: G02B6/4246 , G02B6/4214 , G02B6/4232 , G02B6/4245 , G02B6/4274 , G02B6/428 , G02B6/43 , G02B2006/12061 , G02B2006/12142 , H01L23/49827 , H01L24/17 , H01L24/81 , H01L25/167 , H01L2224/16057 , H01L2224/16225 , H01L2224/1712 , H01L2224/81191 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/1425 , H01L2924/1426 , H01L2924/19041 , H01L2924/19105 , H01L2924/2064 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H04B10/40 , H05K1/0274 , H05K1/181 , H05K3/3436 , H05K2201/10121 , H05K2201/10151 , H05K2201/10378 , H05K2203/049 , Y02P70/611 , Y02P70/613
Abstract: A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.
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公开(公告)号：US20170254968A1
公开(公告)日：2017-09-07
申请号：US15061941
申请日：2016-03-04
Applicant: INPHI CORPORATION
Inventor： Liang DING , Radhakrishnan L. NAGARAJAN , Roberto COCCIOLI
CPC classification number: G02B6/428 , G02B6/13 , G02B6/30 , G02B6/4232 , G02B6/424 , G02B6/4245 , G02B6/4283 , G02B6/4295 , G02B2006/12121 , G02B2006/12142 , H01L21/565 , H01L21/76877 , H01L24/11 , H01L24/81 , H01L25/167 , H01L2224/11334 , H01L2224/12105 , H01L2224/13014 , H01L2224/13016 , H01L2224/16146 , H01L2224/16227 , H01L2224/81191 , H01L2924/06 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/1205 , H01L2924/141 , H01L2924/1426 , H01L2924/1433
Abstract: An optical transceiver by hybrid multichip integration. The optical transceiver includes a PCB with a plurality of prefabricated surface bonding sites. A first chip includes a FOWLP package of multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer is disposed on the PCB by respectively bonding a plurality of conductor balls between the dielectric redistribution layer and the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) in the dielectric molding layer. The optical transceiver further includes a second chip configured as a Sipho die comprising photonics devices embedded in a SOI wafer substantially free from any electronics device process. The second chip is stacked over the first chip with multiple conductor bumps being bonded respectively to the soldering material in the multiple TMVs.
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