公开(公告)号：US20080242015A1

公开(公告)日：2008-10-02

申请号：US11691691

申请日：2007-03-27

申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Jae-eon Park

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/823871 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.

摘要翻译： 形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。 覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第 具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。 然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。 此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

公开(公告)号：US20080188046A1

公开(公告)日：2008-08-07

申请号：US11671158

申请日：2007-02-05

申请人： Matthias Hierlemann ,  Ja-Hum Ku

发明人： Matthias Hierlemann ,  Ja-Hum Ku

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/268 ,  G21K5/00

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7846

摘要： A method and apparatus for crystallizing a semiconductor that includes a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation, comprising amorphizing at least a portion of the second layer, applying a stress to the second layer and heating the second layer above a recrystallization temperature.

摘要翻译： 一种用于结晶半导体的方法和装置，其包括具有第一晶格取向的第一层和具有第二晶格取向的第二层，包括使第二层的至少一部分非晶化，向第二层施加应力并加热 在再结晶温度以上的第二层。

公开(公告)号：US20080029823A1

公开(公告)日：2008-02-07

申请号：US11870573

申请日：2007-10-11

申请人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Teh

发明人： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Teh

IPC分类号： H01L29/94 ,  G21G5/00

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/268 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/7843

摘要： In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

摘要翻译： 在具有用于改善电子迁移率的双应力衬垫的半导体器件中，双应力衬垫包括形成在PMOSFET上的第一衬垫部分和形成在NMOSFET上的第二衬垫部分。 第一衬里部分具有第一压缩应力，并且第二衬套部分具有小于第一压缩应力的第二压缩应力。 双应力衬垫可以通过在其上形成PMOSFET和NMOSFET的半导体衬底上形成应力衬垫而形成，并且选择性地暴露在NMOSFET上的应力衬垫的一部分。

公开(公告)号：US07317204B2

公开(公告)日：2008-01-08

申请号：US11218397

申请日：2005-09-02

申请人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Wee Lang Tan ,  Sunfei Fang ,  Zhijiong Luo

发明人： Min-chul Sun ,  Ja-hum Ku ,  Brian J. Greene ,  Manfred Eller ,  Wee Lang Tan ,  Sunfei Fang ,  Zhijiong Luo

IPC分类号： H01L23/58

CPC分类号： H01L22/34

摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

摘要翻译： 提供半导体器件的测试结构。 测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域， 第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

公开(公告)号：US20070184649A1

公开(公告)日：2007-08-09

申请号：US11348428

申请日：2006-02-06

申请人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

发明人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole. The first electrically insulating material, which has a relatively high degree of porosity, is then removed from the at least one via hole. This removal step may be performed using a relatively mild ashing process because of the high porosity of the first electrically insulating material.

摘要翻译： 形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。 图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。 在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。 至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。 填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。 选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。 电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。 然后从该至少一个通孔去除具有较高孔隙率的第一电绝缘材料。 由于第一电绝缘材料的高孔隙率，该去除步骤可以使用相对温和的灰化过程进行。

公开(公告)号：US20060163677A1

公开(公告)日：2006-07-27

申请号：US11386644

申请日：2006-03-22

申请人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

发明人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

IPC分类号： H01L29/94

CPC分类号： H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

公开(公告)号：US20060057807A1

公开(公告)日：2006-03-16

申请号：US11269599

申请日：2005-11-09

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31612 ,  H01L27/115

摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.

公开(公告)号：US20060003534A1

公开(公告)日：2006-01-05

申请号：US11147633

申请日：2005-06-08

申请人： Kwan-Jong Roh ,  Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Min-Joo Kim ,  Sung-Kee Han

发明人： Kwan-Jong Roh ,  Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Min-Joo Kim ,  Sung-Kee Han

IPC分类号： H01L21/336

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66545

摘要： A salicide process using a bi-metal layer and method of fabricating a semiconductor substrate using the same are disclosed herein. The salicide process includes forming a main metal layer on a semiconductor substrate containing silicon. A main metal alloy layer containing at least one species of alloy element is formed on the main metal layer. The semiconductor substrate having the main metal layer and the main metal alloy layer is annealed to form a main metal alloy silicide layer. According to an exemplary embodiment of the present invention, the main metal layer may be formed of a nickel (Ni) layer, and the main metal alloy layer may be formed of a nickel tantalum alloy layer. In this case, a nickel tantalum silicide layer having improved thermal stability and electrical characteristics are formed.

摘要翻译： 本文公开了使用双金属层的自对准硅化物工艺和使用其制造半导体衬底的方法。 自对准硅化物工艺包括在含硅的半导体衬底上形成主金属层。 在主金属层上形成含有至少一种合金元素的主金属合金层。 将具有主金属层和主金属合金层的半导体基板退火以形成主金属合金硅化物层。 根据本发明的示例性实施例，主金属层可以由镍（Ni）层形成，并且主金属合金层可以由镍钽合金层形成。 在这种情况下，形成具有改善的热稳定性和电特性的镍硅化钽层。

公开(公告)号：US20050236715A1

公开(公告)日：2005-10-27

申请号：US11148301

申请日：2005-06-09

申请人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim

发明人： Ja-Hum Ku ,  Kwan-Jong Roh ,  Min-Chul Sun ,  Min-Joo Kim

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/24 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/4941 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.

摘要翻译： 提供了用于形成硅化镍层的示例性方法和结合有硅化镍层的半导体器件，其为在450℃以上的温度下进行后续处理提供了更高的稳定性。特别地，硅化镍层由具有少部分 合金化金属如钽，并且表现出减少的附聚并延缓NiSi和NiSi 2 N之间的相变，以抑制薄层电阻的增加并提高使用精细图案的效用。 如所形成的那样，硅化镍层包括主要由镍和硅组成的下层和掺入大部分合金金属的较薄的上层。

公开(公告)号：US06764961B2

公开(公告)日：2004-07-20

申请号：US09992980

申请日：2001-11-06

申请人： Ja-Hum Ku ,  Mahn-Ho Cho ,  Chul-Joon Choi ,  Seong-Jun Heo ,  Jun-Kyu Cho

发明人： Ja-Hum Ku ,  Mahn-Ho Cho ,  Chul-Joon Choi ,  Seong-Jun Heo ,  Jun-Kyu Cho

IPC分类号： H01L2131

CPC分类号： H01L29/4941 ,  H01L21/28088 ,  H01L21/32105 ,  H01L21/823437

摘要： The present invention includes a method of forming a metal gate electrode on which whiskers are not formed after performing a selective oxidation process and a subsequent heating process. The metal gate electrode is formed by forming a metal gate electrode pattern which is comprised of a polysilicon layer and a metal layer, and performing a selective oxidation process. After the selective oxidation process, the metal gate electrode undergoes a subsequent heating treatment. The selective oxidation process is carried out in a nitrogen containing gas ambient, so that a metal oxide layer is minimally formed on the metal layer. As a result, it is prevented from causing whiskers on the metal layer.

摘要翻译： 本发明包括在进行选择氧化处理和随后的加热处理之后形成不形成晶须的金属栅电极的方法。 通过形成由多晶硅层和金属层构成的金属栅电极图案，进行选择氧化处理，形成金属栅电极。 在选择氧化处理之后，金属栅电极进行随后的加热处理。 选择性氧化工艺在含氮气体环境中进行，使得在金属层上最少形成金属氧化物层。 结果，防止在金属层上产生晶须。