中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

110 records (took 0.023 seconds)

    Semiconductor memory device and programming method thereof
    21.
    发明授权
    Semiconductor memory device and programming method thereof 有权
    半导体存储器件及其编程方法

    公开(公告)号：US08427881B2

    公开(公告)日：2013-04-23

    申请号：US12748613

    申请日：2010-03-29

    Applicant: Jae Hoon Jang ,  Jung Dal Choi

    Inventor： Jae Hoon Jang ,  Jung Dal Choi

    IPC: G11C11/4094

    CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/24

    Abstract: A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among the bitlines.

    Abstract translation: 半导体存储器件的编程方法包括：将禁止串的通道充电到提供给公共源极线的预充电电压，并通过向单元串提供字线电压来升压充电通道。 禁止字符串连接到位线之间的程序位线。

    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines
    22.
    发明授权
    Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines 有权
    用于形成具有包括选择线，位线和字线的金属化的半导体器件的方法

    公开(公告)号：US08399308B2

    公开(公告)日：2013-03-19

    申请号：US13236000

    申请日：2011-09-19

    Applicant: Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    Inventor： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

    IPC: H01L21/82

    CPC classification number: H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

    Abstract translation: 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

    Non-volatile memory device and erase method
    25.
    发明授权
    Non-volatile memory device and erase method 有权
    非易失性存储器件和擦除方法

    公开(公告)号：US08054688B2

    公开(公告)日：2011-11-08

    申请号：US12539829

    申请日：2009-08-12

    Applicant: Jae-hun Jeong ,  Soon-moon Jung ,  Han-soo Kim ,  Jae-hoon Jang

    Inventor： Jae-hun Jeong ,  Soon-moon Jung ,  Han-soo Kim ,  Jae-hoon Jang

    IPC: G11C16/04

    CPC classification number: G11C16/16 ,  G11C16/0483

    Abstract: Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float.

    Abstract translation: 提供了一种非易失性存储器件，包括第一和第二垂直堆叠的半导体衬底，在第一和第二半导体衬底上形成为一行的多个非易失性存储单元晶体管，以及连接到第一和第二半导体衬底的栅极的多条字线 多个非易失性存储单元晶体管。 多个非易失性存储单元晶体管被分组成两个或更多个存储单元块，使得第一电压被施加到第一半导体衬底，该第一半导体衬底包括要擦除的第一存储单元块，以及（1）第二电压较小 比不包括第一存储单元块的第二半导体衬底施加大于0V的第一电压，或者（2）不包括第一存储单元块的第二半导体衬底被电浮动。

    NON-VOLATILE MEMORY DEVICES HAVING VERTICAL CHANNEL STRUCTURES AND RELATED FABRICATION METHODS
    26.
    发明申请
    NON-VOLATILE MEMORY DEVICES HAVING VERTICAL CHANNEL STRUCTURES AND RELATED FABRICATION METHODS 审中-公开
    具有垂直通道结构的非易失性存储器件及相关制造方法

    公开(公告)号：US20110227141A1

    公开(公告)日：2011-09-22

    申请号：US13048649

    申请日：2011-03-15

    Applicant: Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang

    Inventor： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang

    IPC: H01L29/792

    CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

    Abstract: A memory device having a vertical channel structure is disclosed. The memory device includes a plurality of gate lines extending substantially parallel to one another along a surface of a substrate, and a connection unit electrically connecting the plurality of gate lines. The connection unit includes a first portion laterally extending along the surface of the substrate, a second portion extending substantially perpendicular to the surface of the substrate, and a supporting insulating layer extending in a cavity defined by the first and second portions of the connection unit. Related fabrication methods are also discussed.

    Abstract translation: 公开了一种具有垂直通道结构的存储器件。 存储器件包括沿衬底的表面基本上彼此平行延伸的多条栅极线，以及电连接多个栅极线的连接单元。 连接单元包括沿基板的表面横向延伸的第一部分，基本上垂直于基板的表面延伸的第二部分，以及在由连接单元的第一和第二部分限定的空腔中延伸的支撑绝缘层。 还讨论了相关制造方法。

    Methods of Forming One Transistor DRAM Devices
    28.
    发明申请
    Methods of Forming One Transistor DRAM Devices 有权
    形成一个晶体管DRAM器件的方法

    公开(公告)号：US20100330752A1

    公开(公告)日：2010-12-30

    申请号：US12842703

    申请日：2010-07-23

    Applicant: Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    Inventor： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC: H01L21/322 ,  H01L21/336

    CPC classification number: H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

    Abstract translation: 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

    Methods of Forming SRAM Devices having Buried Layer Patterns
    30.
    发明申请
    Methods of Forming SRAM Devices having Buried Layer Patterns 有权
    形成具有埋层图案的SRAM器件的方法

    公开(公告)号：US20100120217A1

    公开(公告)日：2010-05-13

    申请号：US12687545

    申请日：2010-01-14

    Applicant: Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    Inventor： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    IPC: H01L21/762

    CPC classification number: H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

    Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

    Abstract translation: SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

Patent Agency Ranking