公开(公告)号：US07804151B2

公开(公告)日：2010-09-28

申请号：US12187419

申请日：2008-08-07

Applicant: Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

Inventor： Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

IPC: H01L23/58

CPC classification number: H01L23/66 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/585 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

Abstract translation: 公开了半导体结构的实施例，半导体结构的设计结构和形成半导体结构的方法。 这些实施例减少谐波并改善有源半导体层和绝缘体上半导体（SOI）晶片的衬底之间的隔离。 具体地，实施例结合了延伸到晶片衬底的完全或部分非晶化区域的沟槽隔离区域。 沟槽隔离区位于位于SOI晶片的有源半导体层之上或之上的至少一个集成电路器件的横向边界的外侧，从而提高了隔离度。 衬底的完全或部分非晶化区域降低衬底迁移率，这降低了衬底/ BOX界面处的电荷层，从而减少了谐波。 可选地，实施例可以在晶片衬底和集成电路器件之间并入气隙，以进一步改善隔离。

公开(公告)号：US20100039644A1

公开(公告)日：2010-02-18

申请号：US12508018

申请日：2009-07-23

Applicant: Sang H. Choi ,  Yeonjoon Park ,  Glen C. King ,  James R. Elliott

Inventor： Sang H. Choi ,  Yeonjoon Park ,  Glen C. King ,  James R. Elliott

IPC: G01J3/28

CPC classification number: G01J3/2823 ,  G01J3/02 ,  G01J3/0256 ,  G01J3/18 ,  G01N21/6452 ,  G01N21/6454 ,  G01N21/648 ,  G01N2021/6421 ,  G01N2021/6478 ,  G02B5/188

Abstract: A spectrometer system includes an array of micro-zone plates (MZP) each having coaxially-aligned ring gratings, a sample plate for supporting and illuminating a sample, and an array of photon detectors for measuring a spectral characteristic of the predetermined wavelength. The sample plate emits an evanescent wave in response to incident light, which excites molecules of the sample to thereby cause an emission of secondary photons. A method of detecting the intensity of a selected wavelength of incident light includes directing the incident light onto an array of MZP, diffracting a selected wavelength of the incident light onto a target focal point using the array of MZP, and detecting the intensity of the selected portion using an array of photon detectors. An electro-optic layer positioned adjacent to the array of MZP may be excited via an applied voltage to select the wavelength of the incident light.

Abstract translation: 光谱仪系统包括每个具有同轴对准的环形光栅的微区域阵列（MZP），用于支撑和照射样品的样品板，以及用于测量预定波长的光谱特性的光子检测器阵列。 样品板响应于入射光发射ev逝波，其激发样品的分子，从而引起次级光子的发射。 检测入射光的所选波长的强度的方法包括将入射光引导到MZP阵列上，使用MZP阵列将入射光的选定波长衍射到目标焦点，并检测所选择的 部分使用光子检测器阵列。 可以通过施加的电压激发邻近MZP阵列定位的电光层，以选择入射光的波长。

公开(公告)号：US20100035403A1

公开(公告)日：2010-02-11

申请号：US12187415

申请日：2008-08-07

Applicant: Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

Inventor： Brennan J. Brown ,  James R. Elliott ,  Alvin J. Joseph ,  Edward J. Nowak

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/764 ,  H01L27/12

Abstract: Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the substrate of a semiconductor-on-insulator (SOI) wafer. Specifically, the embodiments incorporate a trench isolation region extending to a fully or partially amorphized region of the wafer substrate. The trench isolation region is positioned outside lateral boundaries of at least one integrated circuit device located at or above the active semiconductor layer of the SOI wafer and, thereby improves isolation. The fully or partially amorphized region of the substrate reduces substrate mobility, which reduces the charge layer at the substrate/BOX interface and, thereby reduces harmonics. Optionally, the embodiments can incorporate an air gap between the wafer substrate and integrated circuit device(s) in order to further improve isolation.

Abstract translation: 公开了半导体结构的实施例，半导体结构的设计结构和形成半导体结构的方法。 这些实施例减少谐波并改善有源半导体层和绝缘体上半导体（SOI）晶片的衬底之间的隔离。 具体地，实施例结合了延伸到晶片衬底的完全或部分非晶化区域的沟槽隔离区域。 沟槽隔离区位于位于SOI晶片的有源半导体层之上或之上的至少一个集成电路器件的横向边界的外侧，从而提高了隔离度。 衬底的完全或部分非晶化区域降低衬底迁移率，这降低了衬底/ BOX界面处的电荷层，从而减少了谐波。 可选地，实施例可以在晶片衬底和集成电路器件之间并入气隙，以进一步改善隔离。

公开(公告)号：US07558371B2

公开(公告)日：2009-07-07

申请号：US12254150

申请日：2008-10-20

Applicant: Yeonjoon Park ,  Sang Hyouk Choi ,  Glen C. King ,  James R. Elliott

Inventor： Yeonjoon Park ,  Sang Hyouk Choi ,  Glen C. King ,  James R. Elliott

IPC: G01N23/20

CPC classification number: G01N23/207

Abstract: A method provides X-ray diffraction data suitable for integral detection of a twin defect in a strained or lattice-matched epitaxial material made from components having crystal structures having symmetry belonging to different space groups. The material is mounted in an X-ray diffraction (XRD) system. In one embodiment, the XRD system's goniometer angle Ω is set equal to (θB−β) where θB is a Bragg angle for a designated crystal plane of the alloy that is disposed at a non-perpendicular orientation with respect to the {111) crystal plane, and β is the angle between the designated crystal plane and a {111} crystal plane of one of the epitaxial components. The XRD system's detector angle is set equal to (θB+β). The material can be rotated through an angle of azimuthal rotation φ about the axis aligned with the material. Using the detector, the intensity of the X-ray diffraction is recorded at least at the angle at which the twin defect occurs.

Abstract translation: 一种方法提供了适用于由具有属于不同空间群的对称性的晶体结构的组分制成的应变或晶格匹配的外延材料中的双缺陷的积分检测的X射线衍射数据。 该材料安装在X射线衍射（XRD）系统中。 在一个实施例中，XRD系统的测角仪角度Ω被设置为等于（θB-β），其中θB是相对于{111）晶体以非垂直取向设置的合金的指定晶面的布拉格角 平面，β是指定的晶面与外延成分之一的{111}晶面之间的角度。 XRD系统的检测器角度设置为等于（θB+β）。 材料可以围绕与材料对准的轴线旋转方位角旋转角度。 使用检测器，至少以发生双瑕疵的角度记录X射线衍射的强度。

公开(公告)号：US20090103680A1

公开(公告)日：2009-04-23

申请号：US12254150

申请日：2008-10-20

Applicant: Yeonjoon Park ,  Sang Hyouk Choi ,  Glen C. King ,  James R. Elliott

Inventor： Yeonjoon Park ,  Sang Hyouk Choi ,  Glen C. King ,  James R. Elliott

IPC: G01N23/207

CPC classification number: G01N23/207

Abstract: A method provides X-ray diffraction data suitable for integral detection of a twin defect in a strained or lattice-matched epitaxial material made from components having crystal structures having symmetry belonging to different space groups. The material is mounted in an X-ray diffraction (XRD) system. In one embodiment, the XRD system's goniometer angle Ω is set equal to (θB−β) where θB is a Bragg angle for a designated crystal plane of the alloy that is disposed at a non-perpendicular orientation with respect to the {111) crystal plane, and β is the angle between the designated crystal plane and a {111} crystal plane of one of the epitaxial components. The XRD system's detector angle is set equal to (θB+β). The material can be rotated through an angle of azimuthal rotation φ about the axis aligned with the material. Using the detector, the intensity of the X-ray diffraction is recorded at least at the angle at which the twin defect occurs.

Abstract translation: 一种方法提供了适用于由具有属于不同空间群的对称性的晶体结构的组分制成的应变或晶格匹配的外延材料中的双缺陷的积分检测的X射线衍射数据。 该材料安装在X射线衍射（XRD）系统中。 在一个实施例中，XRD系统的测角仪角度Ω被设置为等于（θB-β），其中θB是相对于{111）晶体以非垂直取向设置的合金的指定晶面的布拉格角 平面，β是指定的晶面与外延成分之一的{111}晶面之间的角度。 XRD系统的检测器角度设置为等于（θB+β）。 材料可以围绕与材料对准的轴线旋转方位角旋转角度。 使用检测器，至少以发生双瑕疵的角度记录X射线衍射的强度。

公开(公告)号：US07510802B2

公开(公告)日：2009-03-31

申请号：US11371575

申请日：2006-03-09

Applicant: Sang-Hyon Chu ,  Sang H. Choi ,  Jae-Woo Kim ,  Peter T. Lillehei ,  Yeonjoon Park ,  Glen C. King ,  James R. Elliott, Jr.

Inventor： Sang-Hyon Chu ,  Sang H. Choi ,  Jae-Woo Kim ,  Peter T. Lillehei ,  Yeonjoon Park ,  Glen C. King ,  James R. Elliott, Jr.

IPC: H01M4/52

CPC classification number: H01M4/60 ,  H01M4/04 ,  H01M4/364 ,  H01M4/366 ,  H01M4/48 ,  H01M4/50 ,  H01M4/52

Abstract: A thin-film electrode for a bio-nanobattery is produced by consecutively depositing arrays of a ferritin protein on a substrate, employing a spin self-assembly procedure. By this procedure, a first ferritin layer is first formed on the substrate, followed by building a second, oppositely-charged ferritin layer on the top of the first ferritin layer to form a bilayer structure. Oppositely-charged ferritin layers are subsequently deposited on top of each other until a desired number of bilayer structures is produced. An ordered, uniform, stable and robust, thin-film electrode material of enhanced packing density is presented, which provides optimal charge density for the bio-nanobattery.

Abstract translation: 生物纳米电池的薄膜电极是通过使用自旋自组装方法在基片上连续沉积铁蛋白蛋白的阵列产生的。 通过该过程，首先在衬底上形成第一铁蛋白层，随后在第一铁蛋白层的顶部上构建第二个相对充电的铁蛋白层以形成双层结构。 随后将相对充电的铁蛋白层沉积在彼此的顶部，直到产生所需数量的双层结构。 提出了一种有序，均匀，稳定和稳定的薄膜电极材料，提高了填充密度，为生物纳米电池提供了最佳的电荷密度。

公开(公告)号：US20090072078A1

公开(公告)日：2009-03-19

申请号：US11831233

申请日：2007-07-31

Applicant: Sang H. Choi ,  James R. Elliott, JR. ,  Glen C. King ,  Yeonjoon Park ,  Jae-Woo Kim ,  Sang-Hyon Chu

Inventor： Sang H. Choi ,  James R. Elliott, JR. ,  Glen C. King ,  Yeonjoon Park ,  Jae-Woo Kim ,  Sang-Hyon Chu

IPC: B64B1/06 ,  H01L35/02 ,  H01L35/34

CPC classification number: B64B1/06 ,  B64B1/20 ,  B64B1/30 ,  B64C2201/022 ,  B64C2201/042 ,  B64C2201/122 ,  B64C2201/125 ,  B64C2201/127 ,  H01L35/16 ,  H01L35/22 ,  H01L35/26

Abstract: A new High Altitude Airship (HAA) capable of various extended applications and mission scenarios utilizing inventive onboard energy harvesting and power distribution systems. The power technology comprises an advanced thermoelectric (ATE) thermal energy conversion system. The high efficiency of multiple stages of ATE materials in a tandem mode, each suited for best performance within a particular temperature range, permits the ATE system to generate a high quantity of harvested energy for the extended mission scenarios. When the figure of merit 5 is considered, the cascaded efficiency of the three-stage ATE system approaches an efficiency greater than 60 percent.

Abstract translation: 一个新的高空飞艇（HAA），能够利用创新的机载能量采集和配电系统进行各种扩展应用和任务情景。 电力技术包括先进的热电（ATE）热能转换系统。 多级ATE材料在串联模式下的高效率，各自适合在特定温度范围内的最佳性能，允许ATE系统为扩展的任务情景产生大量的收获能量。 当考虑品质因数5时，三级ATE系统的级联效率接近效率大于60％。

公开(公告)号：US20080116493A1

公开(公告)日：2008-05-22

申请号：US11560893

申请日：2006-11-17

Applicant: James W. Adkisson ,  Marc W. Cantell ,  James R. Elliott ,  James V. Hart ,  Dale W. Martin

Inventor： James W. Adkisson ,  Marc W. Cantell ,  James R. Elliott ,  James V. Hart ,  Dale W. Martin

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.

Abstract translation: 半导体结构包括位于半导体结构内邻近并毗邻地形特征的侧壁的多层隔离物。 多层间隔物包括第一间隔子层，该第一间隔子层包含层叠到包含不同于沉积氧化硅材料的材料的第二间隔子层的沉积氧化硅材料。 第一间隔子层相对于第二间隔物子层凹陷凹陷距离不大于第一间隔子层的厚度（优选为约50至约150埃）。 通过使用相对于热生长的氧化硅材料对沉积的氧化硅材料来说是自限制的化学氧化物去除（COR）蚀刻剂来实现这种凹陷距离。 因此确保了多层间隔层的尺寸完整性和分层避免。

公开(公告)号：US08294989B2

公开(公告)日：2012-10-23

申请号：US12512344

申请日：2009-07-30

Applicant: Yeonjoon Park ,  Sang H. Choi ,  Glen C. King ,  James R. Elliott

Inventor： Yeonjoon Park ,  Sang H. Choi ,  Glen C. King ,  James R. Elliott

IPC: G02B27/44

CPC classification number: G03B27/32 ,  G03F7/70316 ,  G03F7/70383

Abstract: An optical apparatus includes an optical diffraction device configured for diffracting a predetermined wavelength of incident light onto adjacent optical focal points, and a photon detector for detecting a spectral characteristic of the predetermined wavelength. One of the optical focal points is a constructive interference point and the other optical focal point is a destructive interference point. The diffraction device, which may be a micro-zone plate (MZP) of micro-ring gratings or an optical lens, generates a constructive ray point using phase-contrasting of the destructive interference point. The ray point is located between adjacent optical focal points. A method of generating a densely-accumulated ray point includes directing incident light onto the optical diffraction device, diffracting the selected wavelength onto the constructive interference focal point and the destructive interference focal point, and generating the densely-accumulated ray point in a narrow region.

Abstract translation: 光学装置包括被配置为将预定波长的入射光衍射到相邻的光学焦点上的光学衍射装置，以及用于检测预定波长的光谱特性的光子检测器。 其中一个光学焦点是一个建设性的干涉点，另一个光学焦点是一个破坏性的干涉点。 可以是微环形光栅的微区域（MZP）或光学透镜的衍射装置使用相消干涉点的相位对应产生建设性的射线点。 射线点位于相邻的光学焦点之间。 产生密集累积的射线点的方法包括将入射光引导到光学衍射装置上，将所选择的波长衍射到构造干涉焦点和破坏性干涉焦点上，并在狭窄区域中产生密集累积的射线点。

公开(公告)号：US08257491B2

公开(公告)日：2012-09-04

申请号：US12288379

申请日：2008-10-20

Applicant: Yeonjoon Park ,  Sang Hyouk Choi ,  Glen C. King ,  James R. Elliott

Inventor： Yeonjoon Park ,  Sang Hyouk Choi ,  Glen C. King ,  James R. Elliott

IPC: C30B33/06 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: G01N23/207

Abstract: Growth conditions are developed, based on a temperature-dependent alignment model, to enable formation of cubic group IV, group II-V and group II-VI crystals in the [111] orientation on the basal (0001) plane of trigonal crystal substrates, controlled such that the volume percentage of primary twin crystal is reduced from about 40% to about 0.3%, compared to the majority single crystal. The control of stacking faults in this and other embodiments can yield single crystalline semiconductors based on these materials that are substantially without defects, or improved thermoelectric materials with twinned crystals for phonon scattering while maintaining electrical integrity. These methods can selectively yield a cubic-on-trigonal epitaxial semiconductor material in which the cubic layer is substantially either directly aligned, or 60 degrees-rotated from, the underlying trigonal material.

Abstract translation: 开发基于温度依赖性取向模型的生长条件，以使得能够在三面晶体基底的（0001）面上形成[111]取向的立方体IV族，II-V族和II-VI族晶体， 控制使得与多数单晶相比，原生双晶的体积百分比从约40％降低至约0.3％。 本实施例和其它实施例中堆垛层错的控制可以产生基本上没有缺陷的这些材料的单晶半导体，或者具有用于声子散射的具有孪晶晶体的改进的热电材料，同时保持电气完整性。 这些方法可以选择性地产生立方晶三面体外延半导体材料，其中立方体层基本上与下面的三角形材料直接对准或者60度旋转。