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48 条记录 (耗时 0.022 秒)

    Resource power controller
    22.
    发明申请
    Resource power controller 有权
    资源功率控制器

    公开(公告)号：US20080244291A1

    公开(公告)日：2008-10-02

    申请号：US11728993

    申请日：2007-03-28

    申请人： James W. Alexander ,  Krishna Kant ,  Rahul Khanna

    发明人： James W. Alexander ,  Krishna Kant ,  Rahul Khanna

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

    摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for a resource power controller. In some embodiments, an integrated circuit includes a resource power controller to control whether a resource is in an up state or a down state. In some embodiments, the resource power controller heuristically estimates when to return the resource to an up state based, at least in part, on an estimate of a gap size.

    摘要翻译： 本发明的实施例一般涉及用于资源功率控制器的系统，方法和装置。 在一些实施例中，集成电路包括资源功率控制器，用于控制资源是处于向上状态还是处于向下状态。 在一些实施例中，资源功率控制器至少部分地基于间隙大小的估计来启发式地估计什么时候将资源返回到上升状态。

    Pickup truck bed extender apparatus
    23.
    发明授权
    Pickup truck bed extender apparatus 失效

    公开(公告)号：US06513688B2

    公开(公告)日：2003-02-04

    申请号：US09855282

    申请日：2001-05-15

    申请人： Gerard J. Kmita ,  Jeffrey M. Aftanas ,  Donald L. Muñoz ,  James W. Alexander

    发明人： Gerard J. Kmita ,  Jeffrey M. Aftanas ,  Donald L. Muñoz ,  James W. Alexander

    IPC分类号： B60R900

    CPC分类号： B60P3/40 ,  B60R5/041

    摘要： A bed extender apparatus for use with a truck bed of a vehicle such as a pickup truck. The bed extender includes a center wall having a pair of uprights at opposite ends thereof. A pair of end walls are pivotably coupled to the uprights and can be folded down over the center wall when the bed extender is not in use, or attached to sidewalls of the truck bed to place the bed extender in a bed extending configuration. The center wall is secured to an inside surface of a tailgate of the vehicle by a pair of mounting assemblies. The mounting assemblies allow the bed extender to be quickly slidably detached from the truck bed when not needed. The bed extender can also be installed within the truck bed to provide an article restraining function.

    Method and system to improve the operations of a registered memory module
    24.
    发明授权
    Method and system to improve the operations of a registered memory module 有权
    改进注册内存模块操作的方法和系统

    公开(公告)号：US08661284B2

    公开(公告)日：2014-02-25

    申请号：US13741532

    申请日：2013-01-15

    申请人： James W. Alexander ,  Kuljit S. Bains ,  Howard S. David

    发明人： James W. Alexander ,  Kuljit S. Bains ,  Howard S. David

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/12 ,  G06F1/04 ,  G11C5/14 ,  G11C8/00 ,  G06F12/00

    CPC分类号： G06F1/04 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.

    摘要翻译： 一种改善注册内存模块操作的方法和系统。 在本发明的一个实施例中，当登记的存储器模块中的时钟电路被激活时，所登记的存储器模块允许异步读取和写入操作。 在本发明的另一个实施例中，登记的存储器模块允许其时钟电路的启用或禁用，而不会中断其操作。 当注册的存储器模块中的时钟电路被禁用时，可以减少注册的存储器模块的功耗。 在本发明的另一实施例中，允许登记的存储器模块进入或退出异步操作模式，而不进入或退出已注册存储器模块的自刷新或预充电掉电操作模式。

    Synchronized memory channels with unidirectional links
    26.
    发明授权
    Synchronized memory channels with unidirectional links 有权
    具有单向链路的同步存储信道

    公开(公告)号：US07516349B2

    公开(公告)日：2009-04-07

    申请号：US11323345

    申请日：2005-12-29

    申请人： James W. Alexander ,  Rajat Agarwal ,  Pete D. Vogt

    发明人： James W. Alexander ,  Rajat Agarwal ,  Pete D. Vogt

    IPC分类号： G06F1/12 ,  G06F1/00 ,  G06F1/04

    CPC分类号： G06F13/124

    摘要： A memory agent may include a first memory channel interface and a second memory channel, both with unidirectional links, and logic to synchronize a signal processed by the first memory channel interface with a signal processed by the second memory channel interface. An embodiment of a method may include synchronizing a signal on a first memory channel with unidirectional links with a signal on a second memory channel with unidirectional links.

    摘要翻译： 存储器代理可以包括具有单向链路的第一存储器通道接口和第二存储器通道，以及用于将由第一存储器通道接口处理的信号与由第二存储器通道接口处理的信号同步的逻辑。 一种方法的实施例可以包括使第一存储器通道上的信号与具有单向链路的第二存储器通道上的信号的单向链路同步。

    Pickup truck bed extender apparatus
    27.
    发明授权
    Pickup truck bed extender apparatus 失效
    皮卡车加床器

    公开(公告)号：US06540123B1

    公开(公告)日：2003-04-01

    申请号：US09702008

    申请日：2000-10-30

    申请人： Gerard J. Kmita ,  Jeffrey M. Aftanas ,  Donald L. Muñoz ,  James W. Alexander

    发明人： Gerard J. Kmita ,  Jeffrey M. Aftanas ,  Donald L. Muñoz ,  James W. Alexander

    IPC分类号： B60R900

    CPC分类号： B60R5/041 ,  B60P3/40

    摘要： A bed extender apparatus adapted for use with a pickup truck bed to functionally enlarge the useable cargo area within the truck bed when a tailgate is in a lowered position. The bed extender includes a center wall which is pivotably mounted to an inner surface of the tailgate, and which can be pivoted into an upright position once the tailgate is moved into a lowered position. A pair of end walls are pivotably secured to opposite ends of the center wall. Each end wall can be pivoted out to a position extending perpendicular to the center wall once the center wall is in its raised or operative position. Each of the end walls can then be secured to an associated one of the vertical walls of the pickup truck bed. A principal advantage of the bed extender is that the end walls and center wall each include a plurality of members which, when the end walls are folded against the center wall, form an extremely compact arrangement which takes up virtually no appreciable cargo space within the pickup truck bed. The bed extender also forms an extremely aerodynamically efficient structure when in use.

    摘要翻译： 一种床扩展器装置，适于与卡车车床一起使用，以在后挡板处于降低位置时功能地扩大卡车底盘内的可用货物区域。 床延长器包括可枢转地安装到后挡板的内表面的中心壁，并且一旦后挡板移动到降低位置中，该中心壁可以枢转到直立位置。 一对端壁可枢转地固定在中心壁的相对端。 一旦中心壁处于其升高或操作位置，每个端壁可以枢转到垂直于中心壁延伸的位置。 然后可以将每个端壁固定到皮卡车床的垂直壁中相关联的一个。 床垫延伸器的主要优点是端壁和中心壁各自包括多个构件，当端壁相对于中心壁折叠时，多个构件形成非常紧凑的布置，其在拾取器内几乎不占据明显的货物空间 卡车床。 床用延长器在使用时也形成极其空气动力学有效的结构。

    Method and apparatus for synchronizing a JTAG test control signal to an on-chip clock signal
    28.
    发明授权
    Method and apparatus for synchronizing a JTAG test control signal to an on-chip clock signal 失效
    用于将JTAG测试控制信号同步到片上时钟信号的方法和装置

    公开(公告)号：US5434804A

    公开(公告)日：1995-07-18

    申请号：US175792

    申请日：1993-12-29

    申请人： Robert Bock ,  James W. Alexander

    发明人： Robert Bock ,  James W. Alexander

    IPC分类号： G01R31/3185 ,  G06F11/26 ,  H04L7/02 ,  G05B23/02 ,  G06F11/27 ,  H04L7/00

    CPC分类号： H04L7/02 ,  G01R31/318552 ,  G06F11/261

    摘要： A microprocessor is provided with circuitry for receiving JTAG and ICE test control signals through JTAG test ports and for synchronizing the test signals to a chip clock signal. Test signals synchronized to an external JTAG device are processed internally by an ICE of the microprocessor chip once the test signals are synchronized with the chip clock rate. To this end, the microprocessor is provided with a synchronizer which receives the chip clock signal, a JTAG control signal, and a JTAG reset signal, and outputs a synchronized control signal. The synchronizer includes an unclocked SR flip-flop for sampling the JTAG control signal, and two or more DR flip-flops for synchronizing the JTAG control signal to the chip clock signal. The synchronizer may be configured to generate a control signal pulse or a control signal level. The synchronizer is protocol independent, i.e., the clock rate of the JTAG test commands is independent of the chip clock. Hence, no protocol is required to connect the JTAG test command signals to the ICE. In particular, the synchronizer includes an input stage configured for allowing the JTAG control signal to be much slower than the core clock signal or much faster than the core clock signal.

    摘要翻译： 微处理器提供有用于通过JTAG测试端口接收JTAG和ICE测试控制信号并将测试信号同步到芯片时钟信号的电路。 一旦测试信号与芯片时钟速率同步，与外部JTAG器件同步的测试信号由微处理器芯片的ICE内部处理。 为此，微处理器设置有同步器，其接收芯片时钟信号，JTAG控制信号和JTAG复位信号，并输出同步的控制信号。 同步器包括用于对JTAG控制信号进行采样的非锁定SR触发器，以及用于使JTAG控制信号与芯片时钟信号同步的两个或多个DR触发器。 同步器可以被配置为产生控制信号脉冲或控制信号电平。 同步器与协议无关，即JTAG测试命令的时钟速率与芯片时钟无关。 因此，不需要协议将JTAG测试命令信号连接到ICE。 特别地，同步器包括被配置为允许JTAG控制信号比核心时钟信号慢得多或比核心时钟信号快得多的输入级。

    Minimizing the likelihood of slip between the instant a candidate for a break event is generated and the instant a microprocessor is instructed to perform a break, without missing breakpoints
    29.
    发明授权
    Minimizing the likelihood of slip between the instant a candidate for a break event is generated and the instant a microprocessor is instructed to perform a break, without missing breakpoints 失效
    最小化在休息事件的候选者之间产生滑动的可能性，并且指示微处理器执行中断的瞬间，而不丢失断点

    公开(公告)号：US5383192A

    公开(公告)日：1995-01-17

    申请号：US996036

    申请日：1992-12-23

    申请人： James W. Alexander

    发明人： James W. Alexander

    IPC分类号： G06F11/26 ,  G06F11/22

    CPC分类号： G06F11/261

    摘要： An in-circuit emulator on an integrated circuit chip having an input pin for externally triggering on-chip break mechanisms. A break logic having an arm input is connected to an instruction pointer counter (IP counter). The break logic matches the IP counter to an instruction execution address. A counter is provided that once started runs a period of time and then shuts itself off, the length of the period of time being equal to the amount of time it takes for the break logic to arm after assertion of the arm input. A break logic control is connected to the input pin activates the arm input in response to signals on the input pin. The break logic control also starts the counter. The break logic control includes means connected to the arm input, to the counter, to the match output, and to the abrupt break input, operative upon the condition that the match output is asserted during the period of time, to inhibit the assertion of the arm input by the break logic control and asserts the abrupt break input to the abrupt break logic.

    摘要翻译： 集成电路芯片上的在线仿真器，具有用于外部触发片上断开机制的输入引脚。 具有臂输入的断开逻辑连接到指令指针计数器（IP计数器）。 中断逻辑将IP计数器与指令执行地址进行匹配。 提供了一个计数器，一旦启动运行一段时间，然后自动关闭，该时间段的长度等于断言逻辑在断言手臂输入之后所需的时间量。 断路逻辑控制连接到输入引脚，响应输入引脚上的信号激活臂输入。 中断逻辑控制也启动计数器。 断路逻辑控制包括连接到臂输入，计数器，匹配输出和突发中断输入的装置，该功能在该时间段期间匹配输出被断言的条件下操作，以阻止 通过断开逻辑控制进行臂输入，并断言突发断点输入到突发断点逻辑。