公开(公告)号：US08730313B2

公开(公告)日：2014-05-20

申请号：US12689504

申请日：2010-01-19

Applicant: Kenji Numata

Inventor： Kenji Numata

IPC: A62B1/04

CPC classification number: A61B1/05 ,  A61B1/00039 ,  A61B1/0005 ,  A61B1/00105

Abstract: An endoscope apparatus includes: a reading unit which reads video data and control data from a recording medium, the recording medium containing the video data including a plurality of image data and the control data used to control a measurement operation; a measuring unit which performs the measurement operation on the basis of the image data of the video data read by the reading unit; and a control unit which controls the measuring unit on the basis of the control data read by the reading unit.

Abstract translation: 内窥镜装置包括：读取单元，其从记录介质读取视频数据和控制数据，所述记录介质包含包含多个图像数据的视频数据和用于控制测量操作的控制数据; 测量单元，其基于由读取单元读取的视频数据的图像数据执行测量操作; 以及控制单元，其基于由读取单元读取的控制数据来控制测量单元。

公开(公告)号：US20130308663A1

公开(公告)日：2013-11-21

申请号：US13474053

申请日：2012-05-17

Applicant: JEFFREY R. CHEN ,  Kenji Numata ,  Stewart T. Wu ,  Guangning Yang

Inventor： JEFFREY R. CHEN ,  Kenji Numata ,  Stewart T. Wu ,  Guangning Yang

IPC: H01S3/10

CPC classification number: H01S5/06256 ,  G01S7/484 ,  H01S3/1304 ,  H01S3/1305 ,  H01S5/0687

Abstract: An apparatus and method is provided to enable precision and fast laser frequency tuning. For instance, a fast tunable slave laser may be dynamically offset-locked to a reference laser line using an optical phase-locked loop. The slave laser is heterodyned against a reference laser line to generate a beatnote that is subsequently frequency divided. The phase difference between the divided beatnote and a reference signal may be detected to generate an error signal proportional to the phase difference. The error signal is converted into appropriate feedback signals to phase lock the divided beatnote to the reference signal. The slave laser frequency target may be rapidly changed based on a combination of a dynamically changing frequency of the reference signal, the frequency dividing factor, and an effective polarity of the error signal. Feed-forward signals may be generated to accelerate the slave laser frequency switching through laser tuning ports.

Abstract translation: 提供了一种能够实现精确和快速的激光频率调谐的装置和方法。 例如，使用光锁相环可以将快速可调的从属激光器动态地偏置锁定到参考激光线。 从属激光器与参考激光线进行外差，以产生随后频率分频的节拍。 可以检测分割的拍子和参考信号之间的相位差，以产生与相位差成比例的误差信号。 误差信号被转换成适当的反馈信号，以将分频的beatnote锁定到参考信号。 可以基于参考信号的动态变化的频率，分频因子和误差信号的有效极性的组合来快速地改变从属激光频率目标。 可以产生前馈信号，以通过激光调谐端口加速从属激光器频率切换。

公开(公告)号：US20130093908A1

公开(公告)日：2013-04-18

申请号：US13609844

申请日：2012-09-11

Applicant: Kenji NUMATA

Inventor： Kenji NUMATA

IPC: H04N5/225

CPC classification number: H04N5/23232 ,  H04N5/23209 ,  H04N2005/2255

Abstract: An image processing apparatus of the present invention includes: a video input section to which live video obtained by picking up an image of an object is inputted; a frame interpolation processing section which, by inserting an interpolated image between images of frames constituting the live video, performs processing for generating and outputting interpolated video of a frame rate set in advance; and a control section which, when an instruction for freezing video displayed on a display section is made, operates so as to cause a still image of a frame constituting the live video to be displayed on the display section.

Abstract translation: 本发明的图像处理装置包括：输入通过拍摄对象的图像而获得的实况视频的视频输入部; 帧内插处理部，通过在构成实时视频的帧的图像之间插入内插图像，执行用于生成并输出预先设定的帧速率的内插视频的处理; 以及控制部分，当进行用于冻结显示在显示部分上的视频的指令时，操作以使得构成实时视频的帧的静止图像显示在显示部分上。

公开(公告)号：US07058863B2

公开(公告)日：2006-06-06

申请号：US10131194

申请日：2002-04-25

Applicant: Toshiyuki Kouchi ,  Makoto Takahashi ,  Kenji Numata

Inventor： Toshiyuki Kouchi ,  Makoto Takahashi ,  Kenji Numata

IPC: G11C29/00

CPC classification number: H01L27/0203 ,  G11C5/025 ,  H01L27/10897 ,  H01L27/118

Abstract: A semiconductor integrated circuit including a region of a memory macro function block is divided into memory core function block and interface function block regions. The interface function block includes a test circuit, a command decoder for a test, an address decoder for the test, a memory core input/output circuit which inputs a command and address into the memory core function block and transmits!receives data with the memory core function block, a configuration memory block in which information of a memory capacity of the memory core function block and configuration of a memory core is stored, and a configuration memory block which controls a data path and address path of the memory core function block based on the stored information.

Abstract translation: 包括存储器宏功能块的区域的半导体集成电路被分为存储器核心功能块和接口功能块区域。 接口功能块包括测试电路，用于测试的命令解码器，用于测试的地址解码器，存储器核心输入/输出电路，其将命令和地址输入到存储器核心功能块中并发送！与存储器接收数据 核心功能块，其中存储有存储器核心功能块的存储器容量和存储器核心的配置的信息的配置存储器块，以及基于存储器核心功能块的数据路径和地址路径的配置存储器块 对存储的信息。

公开(公告)号：US5970015A

公开(公告)日：1999-10-19

申请号：US102627

申请日：1998-06-23

Applicant: Kenji Numata ,  Masaki Ogihara

Inventor： Kenji Numata ,  Masaki Ogihara

IPC: G11C11/406 ,  G11C5/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/44 ,  G11C29/50 ,  G11C29/56 ,  H01L27/10 ,  G11C8/00

CPC classification number: G11C11/4085 ,  G11C11/406 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50016 ,  G11C5/00 ,  G11C5/06 ,  G11C7/1018 ,  G11C11/401

Abstract: A semiconductor integrated circuit device capable of changing the product specification. The semiconductor integrated circuit device includes an integrated circuit section containing a first circuit section having a first function and a second circuit section having a second function, and an active signal generator means for producing an active signal for activating the first circuit section or the second circuit section. To change the product specification, the integrated circuit device further includes a receiving for taking in a decision signal for determining the product specification a, switching signal generator, connected to the receiving device, for producing a switching signal for changing the product specification based on the decision signal, and switching device which receives the active signal and the switching signal, and which, based on the switching signal, changes the supply of the active signal to either the first circuit section or to the second circuit section.

Abstract translation: 能够改变产品规格的半导体集成电路装置。 半导体集成电路器件包括集成电路部分，其包含具有第一功能的第一电路部分和具有第二功能的第二电路部分;以及主动信号发生器装置，用于产生用于激活第一电路部分或第二电路的有效信号 部分。 为了改变产品规格，集成电路装置还包括用于接收用于确定产品规格a的判定信号的接收，连接到接收装置的切换信号发生器，用于产生用于基于所述接收装置改变产品规格的切换信号 决定信号和接收有源信号和切换信号的开关装置，并且基于开关信号将有源信号的供给改变为第一电路部分或第二电路部分。

公开(公告)号：US5754481A

公开(公告)日：1998-05-19

申请号：US857559

申请日：1997-05-16

Applicant: Tomoaki Yabe ,  Kenji Numata ,  Katsuhiko Sato ,  Ryo Haga ,  Shinji Miyano ,  Tohru Furuyama

Inventor： Tomoaki Yabe ,  Kenji Numata ,  Katsuhiko Sato ,  Ryo Haga ,  Shinji Miyano ,  Tohru Furuyama

IPC: G11C7/10 ,  G11C11/407 ,  G11C7/00

CPC classification number: G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078

Abstract: A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.

Abstract translation: 半导体存储器件包括存储单元阵列，行解码器，位线对，读出放大器，读出放大器控制电路，数据锁存器，传输门，传输门控制电路和写电路。 存储单元阵列具有以阵列形式排列的动态存储单元。 行解码器解码行地址信号以选择存储单元阵列的所需行中的一行。 每个位线对连接到布置在存储单元阵列的相应列上的存储单元的每一个。 读出放大器放大在配对位线上读出的数据，并将数据反馈给配对的位线以保存数据。 读出放大器控制电路控制读出放大器的工作。 数据锁存器锁存读出数据和写入数据。 传输门在数据锁存器和读出放大器之间传送数据。 传输门控制电路控制传输门。 写入电路与时钟信号同步地将数据写入数据锁存器。 在将数据写入存储器单元时，数据预先由写入电路提供给数据锁存器并锁存在数据锁存器中，并且在传输门控制电路控制传输门以向位线对提供数据之后 数据锁存器，读出放大器控制电路激活读出放大器。

公开(公告)号：US5734619A

公开(公告)日：1998-03-31

申请号：US944729

申请日：1992-09-15

Applicant: Kenji Numata ,  Syuso Fujii

Inventor： Kenji Numata ,  Syuso Fujii

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/00

CPC classification number: G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C8/12

Abstract: A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines on the basis of the control signals.

公开(公告)号：US5698876A

公开(公告)日：1997-12-16

申请号：US576477

申请日：1995-12-21

Applicant: Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

Inventor： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

IPC: G11C11/401 ,  G11C11/00 ,  G11C11/4074 ,  G11C29/14 ,  H01L21/82 ,  H01L27/02 ,  H01L27/10 ,  H01L27/118 ,  H01L27/108

CPC classification number: G11C29/14 ,  G11C11/005 ,  G11C11/4074 ,  H01L27/0207 ,  Y10S257/909

Abstract: A semiconductor device of a memory-macro type can be designed within a short time to have a desired storage capacity, which does not occupy a large area, so as to reduce the chip cost. The semiconductor device includes a memory macro having sub-memory macros, each sub-memory macro having a DRAM memory-cell array, and a row decoder and a column decoder for selecting any desired memory-cell from the memory cell of the array. The memory macro also includes a control-section macro having a DC potential generating circuit for generating various DC potentials required to drive the sub-memory macros. At least one of the sub-memory macros is combined with the control-section macro to form the memory macro as a one-chip memory capable of storing an integral multiple of N bits.

Abstract translation: 可以在短时间内设计存储器 - 宏型半导体器件以具有不占用大面积的期望的存储容量，从而降低芯片成本。 半导体器件包括具有子存储器宏的存储器宏，每个子存储器宏具有DRAM存储单元阵列，以及用于从阵列的存储器单元中选择任何所需存储单元的行解码器和列解码器。 存储器宏还包括具有DC电位产生电路的控制部分宏，用于产生驱动子存储器宏所需的各种DC电位。 子存储器宏中的至少一个与控制部分宏组合以形成作为能够存储N位的整数倍的单片存储器的存储器宏。

公开(公告)号：US5559748A

公开(公告)日：1996-09-24

申请号：US438656

申请日：1995-05-09

Applicant: Kenji Numata ,  Masaki Ogihara

Inventor： Kenji Numata ,  Masaki Ogihara

IPC: G11C11/406 ,  G11C5/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/44 ,  G11C29/50 ,  G11C29/56 ,  H01L27/10 ,  G11C7/00

CPC classification number: G11C11/4085 ,  G11C11/406 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50016 ,  G11C5/00 ,  G11C5/06 ,  G11C7/1018 ,  G11C11/401

Abstract: A semiconductor integrated circuit capable of changing a product specification comprises a first circuit section having a first function, a second circuit section having a second function, and active signal generator means for producing an active signal for activating either the first circuit section or the second circuit section. To change the product specification, the integrated circuit further comprises means for receiving a decision signal, switching signal generator means, connected to said receiving means, for producing a switching signal for changing the product specification according to the decision signal, and switching means for receiving the active signal and the switching signal and for supplying the active signal to either the first circuit section or the second circuit section according to the switching signal.

Abstract translation: 能够改变产品规格的半导体集成电路包括具有第一功能的第一电路部分，具有第二功能的第二电路部分和用于产生用于激活第一电路部分或第二电路的有源信号的有源信号发生器装置 部分。 为了改变产品规格，集成电路还包括用于接收决定信号的装置，连接到所述接收装置的切换信号发生装置，用于根据判定信号产生用于改变产品规格的切换信号，以及接收装置 有源信号和切换信号，并根据切换信号将有效信号提供给第一电路部分或第二电路部分。

公开(公告)号：US5555523A

公开(公告)日：1996-09-10

申请号：US556148

申请日：1995-11-09

Applicant: Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano ,  Kenji Numata

Inventor： Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano ,  Kenji Numata

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C11/4091 ,  G11C11/4094

Abstract: A semiconductor memory device comprises a plurality of memory cells including at least a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell and paired with the first bit line, an equalizer connected between the first and second bit lines, an amplifier connected between the first and second bit lines, a first driving signal line connected to the amplifier and drives the amplifier, a second driving signal line connected to the amplifier and paired with the first driving signal line, a driver for driving the amplifier and connected to the first and second driving signal lines and containing a precharger for presetting the potentials of the first and second driving signal lines to a predetermined precharge potential and a driving signal supply circuit for supplying a driving signal to the first and second driving signal lines, and a control circuit for controlling the equalizer and the driver, wherein the control circuit controls the equalizer and the precharger independently so that the precharger continues supplying the precharge potential to the first and second driving signal lines until essentially immediately before the driving signal supply circuit supplies the driving signal to the first and second driving signal lines.

Abstract translation: 半导体存储器件包括至少包括第一存储器单元和第二存储单元的多个存储器单元，连接到第一存储器单元的第一位线，连接到第二存储单元的第二位线，并与第一位配对 连接在第一和第二位线之间的均衡器，连接在第一和第二位线之间的放大器，连接到放大器并驱动放大器的第一驱动信号线，连接到放大器的第二驱动信号线， 第一驱动信号线，用于驱动放大器并连接到第一和第二驱动信号线并且包含用于将第一和第二驱动信号线的电位预设为预定预充电电位的预充电器的驱动器和用于 向第一和第二驱动信号线提供驱动信号，以及用于控制均衡器和驱动器的控制电路 r，其中控制电路独立地控制均衡器和预充电器，使得预充电器继续向第一和第二驱动信号线提供预充电电位，直到驱动信号提供电路将驱动信号提供给第一和第二驱动信号为止 线条。