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公开(公告)号：US07803639B2
公开(公告)日：2010-09-28
申请号：US11619623
申请日：2007-01-04
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/44
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译： 在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。 形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。 形成覆盖在第一和第二蚀刻停止层上的ILD层。 在ILD层上形成光刻掩模。 光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。 第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。 随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。
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公开(公告)号：US20080308801A1
公开(公告)日：2008-12-18
申请号：US12193288
申请日：2008-08-18
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译： 一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机 结构纳米孔特征。 在无规纳米孔结构化中间层上形成上导电层。 上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。
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23.发明申请HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME 有权高密度平面磁畴壁记忆装置及其形成方法公开(公告)号：US20080243972A1
公开(公告)日：2008-10-02
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： G06F15/02
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。
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24.发明申请Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit 审中-公开利用侧壁间隔件在集成电路中形成磁隧道结公开(公告)号：US20080211055A1
公开(公告)日：2008-09-04
申请号：US12120915
申请日：2008-05-15
申请人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
发明人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
CPC分类号： H01L43/12 , H01L27/222
摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.
摘要翻译： 描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。 根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。 有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。 此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。
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25.发明授权Method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory 有权图案化用于磁阻随机存取存储器的磁性隧道结叠层的方法公开(公告)号：US07211446B2
公开(公告)日：2007-05-01
申请号：US10709999
申请日：2004-06-11
申请人： Michael C. Gaidis , David W. Abraham , Stephen L. Brown , Arunava Gupta , Chanro Park , Wolfgang Raberg
发明人： Michael C. Gaidis , David W. Abraham , Stephen L. Brown , Arunava Gupta , Chanro Park , Wolfgang Raberg
IPC分类号： H01L21/00
CPC分类号： G11C11/16 , H01L27/222 , H01L43/12
摘要： A method of patterning a magnetic tunnel junction (MTJ) stack is provided. According to such method, an MTJ stack is formed having a free layer, a pinned layer and a tunnel barrier layer disposed between the free layer and the pinned layer. A first area of the MTJ stack is masked while the free layer of the MTJ is exposed in a second area. The free layer is then rendered electrically and magnetically inactive in the second area.
摘要翻译： 提供了一种图案化磁性隧道结（MTJ）堆叠的方法。 根据这种方法，形成具有自由层，钉扎层和设置在自由层和被钉扎层之间的隧道势垒层的MTJ堆叠。 MTJ堆叠的第一区域被屏蔽，而MTJ的自由层在第二区域中被暴露。 然后，自由层在第二区域中被电气地且磁性地不起作用。
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公开(公告)号：US08928100B2
公开(公告)日：2015-01-06
申请号：US13168477
申请日：2011-06-24
CPC分类号： H01L43/12 , B82Y40/00 , H01F10/3254 , H01F10/329 , H01F41/307 , H01L43/08
摘要： Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.
摘要翻译： 实施例针对STT MRAM设备。 STT MRAM器件的一个实施例包括参考层，隧道势垒层，自由层和一个或多个导电通孔。 参考层被配置为具有固定的磁矩。 此外，隧道势垒层被配置为使得电子能够通过隧道势垒层在参考层和自由层之间隧穿。 自由层设置在隧道势垒层之下，并被配置为具有用于存储数据的适应性磁矩。 导电通孔设置在自由层下方并连接到电极。 此外，导电通孔的宽度小于自由层的宽度，使得用于存储自由层中的数据的活动STT区域的宽度由导电通孔的宽度限定。
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27.发明授权Spin-torque based memory device with read and write current paths modulated with a non-linear shunt resistor 有权基于旋转力矩的存储器件，具有用非线性分流电阻调制的读和写电流路径公开(公告)号：US08927301B2
公开(公告)日：2015-01-06
申请号：US13552033
申请日：2012-07-18
CPC分类号： H01L27/224 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/5607 , H01L27/24 , H01L43/08 , H01L45/04 , H01L45/145
摘要： A fabrication method includes forming a spin-polarizing layer, a spin transport layer on the spin polarizing layer on a substrate, a free layer magnet on the spin transport layer, a non-magnetic layer on the spin polarizing layer, a reference layer on the non-magnetic layer, and a hard mask layer on the reference layer, etching the hard mask layer and forming a read portion including the reference layer, the nonmagnetic layer and the free layer magnet, forming a nonlinear resistor layer on surfaces of the spin transport layer, the spacers, and the hard mask layer, etching the nonlinear resistor layer, the spin transport layer, and the spin polarizing layer and forming a write portion including the spin transport layer and the spin polarizing layer, forming an interlevel dielectric layer, forming a trench, exposing an upper surface of the reference layer of the read and write portions.
摘要翻译： 一种制造方法包括在基底上的自旋偏振层上形成自旋极化层，自旋传输层，自旋传输层上的自由层磁体，自旋极化层上的非磁性层， 非磁性层和硬掩模层，蚀刻硬掩模层并形成包括参考层，非磁性层和自由层磁体的读取部分，在自旋输送的表面上形成非线性电阻层 蚀刻非线性电阻层，自旋传输层和自旋偏振层，形成包括自旋传输层和自旋极化层的写入部分，形成层间电介质层，形成层间绝缘层 沟槽，暴露读取和写入部分的参考层的上表面。
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28.发明申请MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS 审中-公开具有合成抗真菌储存层的磁性随机存取存储器公开(公告)号：US20140033516A1
公开(公告)日：2014-02-06
申请号：US13566130
申请日：2012-08-03
IPC分类号： G11B5/84
CPC分类号： G11C11/161 , H01L43/08 , H01L43/12 , Y10T29/49021 , Y10T29/49043 , Y10T29/49044 , Y10T29/49048 , Y10T29/49052
摘要： A method for fabricating a synthetic antiferromagnetic device, includes depositing a reference layer on a first tantalum layer and including depositing a first cobalt iron boron layer, depositing a second cobalt iron boron layer on the first cobalt iron boron layer, depositing a second Ta layer on the second cobalt iron boron layer, depositing a magnesium oxide spacer layer on the reference layer and depositing a cap layer on the magnesium oxide spacer layer.
摘要翻译： 一种用于制造合成反铁磁性器件的方法，包括在第一钽层上沉积参考层，并且包括沉积第一钴铁硼层，在第一钴铁硼层上沉积第二钴铁硼层，在第一钴铁硼层上沉积第二Ta层 第二钴铁硼层，在参考层上沉积氧化镁间隔层并在氧化镁间隔层上沉积覆盖层。
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29.发明申请MAGNETIC TUNNEL JUNCTION SELF-ALIGNMENT IN MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICES 审中-公开磁性隧道连接自动对位在磁性域移位寄存器存储器件公开(公告)号：US20140003118A1
公开(公告)日：2014-01-02
申请号：US13539550
申请日：2012-07-02
CPC分类号： G11C19/0808 , G11C11/14 , G11C11/161 , G11C11/1675 , H01F1/0072 , H01F10/3254 , H01F41/308
摘要： A magnetic domain wall shift register memory device includes a nanowire and a magnetic reference layer island disposed on the nanowire, wherein an interface between the nanowire and the magnetic tunnel junction island is a magnetic tunnel junction aligned with a width of the nanowire.
摘要翻译： 磁畴壁移位寄存器存储器件包括纳米线和设置在纳米线上的磁性参考层岛，其中纳米线与磁性隧道结岛之间的界面是与纳米线的宽度对准的磁性隧道结。
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30.发明授权公开(公告)号：US08519497B2
公开(公告)日：2013-08-27
申请号：US13396998
申请日：2012-02-15
申请人： Michael C. Gaidis
发明人： Michael C. Gaidis
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , B82Y10/00 , H01L43/12 , Y10S438/947 , Y10S977/888
摘要： A device comprising a diblock copolymer mask for fabricating a magnetoresistive random access memory (MRAM) includes a magnetic layer; a mask formed on the magnetic layer; a template formed on the mask; and the diblock copolymer mask, the diblock copolymer mask comprising a first plurality of uniform shapes formed on and registered to the template.
摘要翻译： 包括用于制造磁阻随机存取存储器（MRAM）的二嵌段共聚物掩模的器件包括磁性层; 形成在磁性层上的掩模; 掩模上形成的模板; 和二嵌段共聚物掩模，二嵌段共聚物掩模包含形成在模板上并登记到模板上的第一多个均匀形状。
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