公开(公告)号：US6147919A

公开(公告)日：2000-11-14

申请号：US274245

申请日：1999-03-23

申请人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

发明人： Kuninori Kawabata ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Hideki Kanou ,  Ayako Kitamoto ,  Toru Koga ,  Yuki Ishii ,  Akira Kikutake ,  Yuichi Uzawa

IPC分类号： H01L27/10 ,  G11C7/06 ,  G11C7/12 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C7/12

摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.

摘要翻译： 半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器 涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。 读出放大器在每行中分组成读出放大器模块。 只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器 。 本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。 只写列选择线由用于控制读出放大器的信号控制。

公开(公告)号：US5994004A

公开(公告)日：1999-11-30

申请号：US19743

申请日：1998-02-06

申请人： Yasuko Tabata ,  Satoru Asai ,  Toshimi Ikeda ,  Masato Matsumiya

发明人： Yasuko Tabata ,  Satoru Asai ,  Toshimi Ikeda ,  Masato Matsumiya

IPC分类号： G03F1/30 ,  G03F1/68 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F1/30

摘要： A photomask has a plurality of transparent regions defined in an opaque region and classified into first and second groups. Each of the transparent regions belonging to one of the first and second groups is provided with a phase shifter, so that the phase of light transmitted through the transparent region belonging to the first group becomes different from the phase of light transmitted through the transparent region belonging to the second group. The photomask includes: a pair of first transparent regions belonging to the first group and including linear portions disposed in parallel, a virtual straight line interconnecting one ends of the first transparent regions intersecting at a right angle with the extension direction of the linear portions; and a second transparent region belonging to the second group and disposed at the center between, and in parallel to, the linear portions of the pair of first transparent regions, the second transparent region including a linear thickportion and a linear thin portion, the linear thin portion being disposed in an area between the pair of first transparent regions and continuously coupled to the linear thick portion, and a connection portion between the thick and thin portions being indented from the virtual straight line toward the area between the pair of first transparent regions.

摘要翻译： 光掩模具有限定在不透明区域中并被分类为第一和第二组的多个透明区域。 属于第一组和第二组中的一个的透明区域中的每一个设置有移相器，使得透过属于第一组的透明区域的光的相位与透过透明区域的光的相位不同 到第二组。 光掩模包括：属于第一组的一对第一透明区域，并且包括平行设置的直线部分，将与直线部分的延伸方向成直角相交的第一透明区域的一端相互连接的虚拟直线; 以及属于第二组的第二透明区域，并且设置在一对第一透明区域的直线部分之间并且平行于中心，第二透明区域包括线性​​厚度部分和线状薄部分，线性薄片 部分设置在一对第一透明区域之间的区域中并且连续地连接到线状厚部分，并且厚部分和薄部分之间的连接部分从假想直线向着该对第一透明区域之间的区域缩进。

公开(公告)号：US20100321983A1

公开(公告)日：2010-12-23

申请号：US12718819

申请日：2010-03-05

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C11/24 ,  G11C5/14

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US07281155B1

公开(公告)日：2007-10-09

申请号：US09359767

申请日：1999-07-22

申请人： Satoshi Eto ,  Masato Matsumiya ,  Toshimi Ikeda ,  Yuki Ishii ,  Akira Kikutake ,  Kuninori Kawabata

发明人： Satoshi Eto ,  Masato Matsumiya ,  Toshimi Ikeda ,  Yuki Ishii ,  Akira Kikutake ,  Kuninori Kawabata

IPC分类号： H02H3/05

CPC分类号： G11C29/78

摘要： A semiconductor memory device having a shift redundancy function includes a switch circuit for changeably connecting a plurality of decode signal lines decoding an address signal to a plurality of selecting lines and redundancy selecting lines, and executes a switch operation for shifting at least one of a plurality of decode lines in the direction of a first redundancy selecting line positioned at one of the ends among a plurality of selecting lines or a second switch operation for shifting at least one of the decode lines in the direction of a second redundancy selecting line positioned at the other end among the selecting lines or both of the first and second operations when any fault occurs in a plurality of selecting lines. The semiconductor memory device preferably includes two or more first redundancy selecting lines positioned at one of the ends of a plurality of selecting lines, two or more second redundancy selecting lines positioned at the other end, and first and second switch units disposed in two stages. When any fault selecting line occurs, the first switch unit executes a first switch operation for shifting at least one of the decode signal lines in the direction of the first redundancy selecting line or a second switch operation for shifting the same in the direction of the second redundancy selecting line, or the second switch unit executes a third switch operation for shifting at least one decode signal line in the direction of the first redundancy selecting line or a fourth switch operation for shifting it in the direction of the second redundancy selecting line.

摘要翻译： 具有移位冗余功能的半导体存储器件包括用于将解码地址信号的多条解码信号线与多条选择线和冗余选择线可变地连接的开关电路，并且执行用于移位多个选择线和冗余选择线中的至少一个的切换操作 在位于多个选择线中的一端的第一冗余选择线的方向上的解码线的第二切换操作或用于沿着位于所述多个选择线的第二冗余选择线的方向移位至少一条解码线的第二切换操作 在多个选择线中发生任何故障时，选择线中的另一端或第一和第二操作两者。 半导体存储器件优选地包括位于多个选择线的一端的两个或更多个第一冗余选择线，以及位于另一端的两个或更多个第二冗余选择线以及分两个阶段布置的第一和第二开关单元。 当发生任何故障选择线时，第一开关单元执行第一开关操作，用于沿第一冗余选择线的方向移位至少一个解码信号线，或者执行第二开关操作，以使其在第二冗余选择线的方向上移位 冗余选择线或者第二开关单元执行用于在第一冗余选择线的方向上移位至少一个解码信号线的第三开关操作或者用于在第二冗余选择线的方向上移位的第四开关操作。

公开(公告)号：US07079443B2

公开(公告)日：2006-07-18

申请号：US10631752

申请日：2003-08-01

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/08

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US20050270871A1

公开(公告)日：2005-12-08

申请号：US11198225

申请日：2005-08-08

申请人： Yasushige Ogawa ,  Yoshiyuki Ishida ,  Masato Matsumiya

发明人： Yasushige Ogawa ,  Yoshiyuki Ishida ,  Masato Matsumiya

IPC分类号： H01L27/04 ,  G01R31/3167 ,  H01L21/822 ,  H03M1/10 ,  H03M1/66 ,  G11C7/00

CPC分类号： H03M1/1019 ,  G01R31/3167 ,  H03M1/66

摘要： It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.

摘要翻译： 本发明旨在提供一种半导体集成电路器件的半导体集成电路器件和调整方法，该半导体集成电路器件能够调整从内置的模拟信号产生部分输出的模拟信号而不将其输出为模拟值。 从输入调整信号AD的模拟信号生成部3输出模拟信号AOUT。 模拟信号AOUT被输入到判断部分1，在判定部分1中，以预定值进行比较和判断，然后输出判断信号JG。 判断信号JG作为内部信号作用于预定信号存储部分4，并且调节信号AD被取出到预定信号存储部分4.此外，判断信号JG通过外部端子T 2作为数字信号输出， 外部测试器装置获取调整信号并将获取的调节信号存储在预定信号存储部分4中。因此，可以将模拟信号调整为模拟值而不输出到外部，并且可以使用简单的测试装置进行调整测试， 根据简单的测试方法准确快速。

公开(公告)号：US06909644B2

公开(公告)日：2005-06-21

申请号：US09791815

申请日：2001-02-26

申请人： Shinya Fujioka ,  Hitoshi Ikeda ,  Masato Matsumiya

发明人： Shinya Fujioka ,  Hitoshi Ikeda ,  Masato Matsumiya

IPC分类号： G11C11/409 ,  G11C11/00 ,  G11C11/401 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/4013

摘要： The present invention provides a semiconductor memory device of a twin-storage type having an operation control method and a circuit structure that achieve a higher process rate, a less power consumption, and a smaller chip area. This semiconductor memory device includes bit lines in pairs, a sense amplifier connected to each pair of the bit lines, a first memory cell connected to one bit line of each pair of the bit lines, a second memory cell that is connected to the other bit line of each pair of the bit lines and stores the inverted data of the data stored in the first memory cell. This semiconductor memory device is characterized by not having means to pre-charge the bit lines to a predetermined potential. The semiconductor memory device of the present invention is also characterized by including a control circuit that controls the sense amplifier to start a pull-down operation after starting a pull-up operation.

摘要翻译： 本发明提供一种双存储型半导体存储器件，其具有实现更高处理速率，更少功耗和更小芯片面积的操作控制方法和电路结构。 该半导体存储器件包括成对的位线，连接到每对位线的读出放大器，连接到每对位线的一个位线的第一存储器单元，连接到另一个位的第二存储器单元 并且存储存储在第一存储单元中的数据的反相数据。 该半导体存储器件的特征在于没有将位线预充电到预定电位的装置。 本发明的半导体存储器件的特征还在于包括控制电路，其控制读出放大器在开始上拉操作之后开始下拉操作。

公开(公告)号：US06643805B1

公开(公告)日：2003-11-04

申请号：US09568123

申请日：2000-05-10

申请人： Akira Kikutake ,  Masato Matsumiya ,  Satoshi Eto ,  Kuninori Kawabata

发明人： Akira Kikutake ,  Masato Matsumiya ,  Satoshi Eto ,  Kuninori Kawabata

IPC分类号： G11C2900

CPC分类号： G11C29/40 ,  G11C2029/2602

摘要： The present invention is a memory circuit which selects N number of segments out of M number of segments (N

摘要翻译： 本发明是在正常读取期间从M个片段（N

公开(公告)号：US06618320B2

公开(公告)日：2003-09-09

申请号：US10316121

申请日：2002-12-11

申请人： Masatomo Hasegawa ,  Kaoru Mori ,  Masato Matsumiya

发明人： Masatomo Hasegawa ,  Kaoru Mori ,  Masato Matsumiya

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

摘要： A semiconductor memory device is provided with a clock generation circuit that generates a first clock that has the same frequency and phase as an external clock, and a second clock that has the same frequency as the external clock but a phase a quarter phase shifted, and the first clock and the second clock are supplied to the two DDR-DRAMs as clocks so that the two DDR-DRAMs can operate in a state of being a quarter phase shifted from each other. A data output section outputs data respectively for time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge of the first or the second clock and brings a data output circuit into a high impedance state for other time periods.

摘要翻译： 半导体存储器件设置有产生与外部时钟具有相同频率和相位的第一时钟的时钟产生电路和具有与外部时钟相同频率但是相位四分之一相位偏移的第二时钟，以及 第一时钟和第二时钟作为时钟提供给两个DDR DRAM，使得两个DDR-DRAM可以在相互偏移的四分之一相的状态下操作。 数据输出部分分别从第一或第二时钟的前沿和后沿之后的固定相位的点分别输出对应于四分之一相位的时间段的数据，并将数据输出电路在其他时间段内变为高阻抗状态 。

公开(公告)号：US06515927B2

公开(公告)日：2003-02-04

申请号：US10067236

申请日：2002-02-07

申请人： Ayako Kitamoto ,  Masato Matsumiya

发明人： Ayako Kitamoto ,  Masato Matsumiya

IPC分类号： G11C700

CPC分类号： G11C11/409 ,  G11C7/10 ,  G11C2207/002 ,  G11C2207/065 ,  G11C2207/108

摘要： During a read operation, data read from memory cells onto bit lines are amplified simultaneously by sense amplifiers and outputted to the exterior of a memory. In this operation, a data control circuit outputs to the exterior all the data read from the memory cells onto the bit lines and amplified simultaneously by the sense amplifiers. During a write operation, data supplied from the exterior to the bit lines are amplified by the sense amplifiers and written into the memory cells. In this operation, the data control circuit writes into the memory cells all the data inputted from the exterior and amplified simultaneously by the sense amplifiers. Since all the data amplified simultaneously by the sense amplifiers are inputted/outputted from/to the exterior, the data transfer rate of the input/output data can be improved and the power consumption per unit amount of transferred data can be reduced.

摘要翻译： 在读取操作期间，从存储器单元读取到位线上的数据被读出放大器同时放大并输出到存储器的外部。 在该操作中，数据控制电路将从存储单元读取的所有数据输出到位线，并由读出放大器同时放大。 在写操作期间，从外部向位线提供的数据由读出放大器放大并写入存储单元。 在该操作中，数据控制电路将从外部输入的所有数据写入存储单元，并由读出放大器同时放大。 由于由读出放大器同时放大的全部数据从外部输入/输出，因此可以提高输入/输出数据的数据传送速率，并且可以减少每单位传送数据量的功耗。