公开(公告)号：US20210005256A1

公开(公告)日：2021-01-07

申请号：US16525546

申请日：2019-07-29

Applicant: Microchip Technology Inc.

Inventor： John L. McCollum ,  Fengliang Xue

IPC: G11C13/00

Abstract: A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.

公开(公告)号：US10797686B1

公开(公告)日：2020-10-06

申请号：US16557866

申请日：2019-08-30

Applicant: Microchip Technology Inc.

Inventor： Morten Terstrup ,  Thomas Joergensen

IPC: H03K5/135 ,  H04L7/033 ,  H03L7/085

Abstract: A phase predictor to accurately detect and predict the phase relationship between two clocks running at different frequencies. The phase relationship can be used to record the transmission and reception times of Ethernet frames transmitted over a transmission medium with very high accuracy.

公开(公告)号：US10149357B2

公开(公告)日：2018-12-04

申请号：US15437081

申请日：2017-02-20

Applicant: Microchip Technology Inc.

Inventor： Scott Lynch

IPC: H05B33/08

Abstract: Employed within an LED driver operating from the AC power line, the invention controls both input current and output power. With this regulation circuit, input current appears purely resistive, precisely tracking the input voltage waveshape. At the same time, it provides good line regulation and inherent phase dimmer compatibility, requiring no special circuitry to detect and handle a dimmer.

公开(公告)号：US20180126417A9

公开(公告)日：2018-05-10

申请号：US14045689

申请日：2013-10-03

Applicant: Microchip Technology Inc.

Inventor： Jimes LEI ,  Ching CHU

IPC: B06B1/02

CPC classification number: B06B1/0215

Abstract: An electrical waveform generating circuit has a pair of Pulse Amplitude Controlled Switching Current Sources (PACS). A gate pulse driver circuit is coupled to an input of each of the pair of PACS for sending gate pulses for driving the pair of PACS. A digital-to-analog converter (DAC) circuit is coupled to the gate pulse driver circuit for controlling amplitudes of the gate pulses. A transducer is coupled to the PACS.

公开(公告)号：US20170104481A1

公开(公告)日：2017-04-13

申请号：US15265341

申请日：2016-09-14

Applicant: Microchip Technology Inc.

Inventor： Isaac Ko ,  Ka Wai Ho ,  Wan Tim Chan

IPC: H03K17/16 ,  A61B8/00 ,  A61B8/08

CPC classification number: H03K17/161 ,  A61B8/4483 ,  A61B8/469 ,  A61B8/485 ,  A61B8/546 ,  H03K17/6874 ,  H03K17/693 ,  H03K2217/0054 ,  H04B1/48

Abstract: An improved analog switch for use in an ultrasound elastography probe is disclosed. The improved analog switch results in less heat dissipation compared to prior art analog switches.

公开(公告)号：US09590613B2

公开(公告)日：2017-03-07

申请号：US14742571

申请日：2015-06-17

Applicant: Microchip Technology Inc.

Inventor： Alexander Mednik ,  Rohit Tirumala ,  Marc Tan ,  Simon Krugly

IPC: G05F1/00 ,  H03K17/16 ,  H02M3/158 ,  H02M1/08

CPC classification number: H03K17/162 ,  H02M1/08 ,  H02M3/1584 ,  H02M2003/1586

Abstract: A comparator sense input is disconnected from a current sense resistor for the duration of a switching transition in an adjacent channel(s). Instead, the sense input receives a signal of the magnitude and the slew rate sampled prior to the transition.

Abstract translation: 在相邻信道中的切换转换的持续时间内，比较器检测输入与电流检测电阻断开。 相反，感测输入接收在转换之前采样的幅度和转换速率的信号。

公开(公告)号：US20160212812A9

公开(公告)日：2016-07-21

申请号：US13756060

申请日：2013-01-31

Applicant: Microchip Technology, Inc.

Inventor： Alexander Mednik ,  Rohit Tirumala

IPC: H05B33/08

CPC classification number: H05B33/0839 ,  H05B33/0815 ,  H05B33/0848

Abstract: A circuit for powering of a Light Emitting Diode (LED) string has a switching power converter. A brightness control circuit is coupled to the switching power converter to allow a duration of a conductive state of the power converter to exceed a duration of a conductive state of the LED string for maintaining a current magnitude in the LED string constant.

Abstract translation: 用于为发光二极管（LED）串供电的电路具有开关功率转换器。 亮度控制电路耦合到开关功率转换器，以允许功率转换器的导通状态的持续时间超过LED串的导通状态的持续时间，以维持LED串中的电流幅值恒定。

公开(公告)号：US20150340435A1

公开(公告)日：2015-11-26

申请号：US14727768

申请日：2015-06-01

Applicant: Microchip Technology Inc.

Inventor： Benedict C.K. Choy ,  Ching Chu ,  Haibing (Robin) Liu ,  Ming-Yuan Yeh

IPC: H01L29/06 ,  H01L27/088 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L29/0642 ,  H01L23/481 ,  H01L23/49575 ,  H01L23/525 ,  H01L24/06 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7827 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements.

Abstract translation: 电路模块包括具有表面的管芯附接垫和围绕表面的多个引线。 非导电粘合剂在表面上。 多个电子电路管芯在管芯附着垫的表面上。 每个模具具有顶表面和底表面，底表面在粘合剂上。 顶表面具有多个接合焊盘。 第一电子电路管芯具有将第一接合焊盘连接到第二接合焊盘的导电材料的至少一个布线路径。 第一接合线将第二电子电路管芯的接合焊盘连接到第一电子管芯的第一接合焊盘。 第二接合线将第一电子电路管芯的第二接合焊盘连接到引线。 在其中一个裸片包含垂直电路元件的情况下，其中掺杂层沿着该层的底表面形成端子，填充有掺杂多晶硅的沟槽从顶表面延伸到端子以连接至端子。 掺杂多晶硅填充的沟槽还用于隔离和分离不同的电路元件。

公开(公告)号：US12175363B2

公开(公告)日：2024-12-24

申请号：US17089891

申请日：2020-11-05

Applicant: Microchip Technology Inc.

Inventor： Lorenzo Zuolo ,  Rino Micheloni

IPC: G06N3/08 ,  G06F3/06 ,  G06N3/04 ,  G06N5/04 ,  G06N20/00 ,  G11C11/54 ,  G11C16/26

Abstract: A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.

公开(公告)号：US11843393B2

公开(公告)日：2023-12-12

申请号：US17952240

申请日：2022-09-24

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1111 ,  H03M13/611

Abstract: A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.