公开(公告)号：US07235485B2

公开(公告)日：2007-06-26

申请号：US11251180

申请日：2005-10-14

Applicant: Jun-keun Kwak ,  Roland Hampp

Inventor： Jun-keun Kwak ,  Roland Hampp

IPC: H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76895

Abstract: Provided is a method of manufacturing a semiconductor device with enhanced electrical characteristics. The method includes disposing a substrate on a substrate support in a process chamber, pre-heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 60 seconds or more, forming a silicon protective layer on the substrate by supplying a silicon source gas into the process chamber and heating the substrate on the substrate support adjusted to a temperature from 300 to 400° C. for 10 seconds or more, and forming a tungsten layer on the silicon protective layer.

Abstract translation: 提供一种制造具有增强的电气特性的半导体器件的方法。 该方法包括将衬底设置在处理室中的衬底支撑件上，预热衬底上的衬底，调节到300-400℃的温度达60秒以上，在衬底上形成硅保护层，通过 将硅源气体供应到处理室中，并加热调节至300-400℃温度的衬底支撑体上的衬底10秒以上，并在硅保护层上形成钨层。

公开(公告)号：US08643126B2

公开(公告)日：2014-02-04

申请号：US13365418

申请日：2012-02-03

Applicant: Roland Hampp

Inventor： Roland Hampp

IPC: H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

Abstract translation: 公开了形成自对准硅化物触点的结构和方法。 该结构包括设置在有源区上的栅电极，设置在栅极上的衬垫和有源区的至少一部分，设置在衬垫上的绝缘层。 第一接触插塞设置在绝缘层和衬垫中，第一接触插头设置在有源区域的一部分上方并与其接触，第一接触插塞包括第一导电材料。 第二接触插塞设置在绝缘层和衬垫中，第二接触插塞设置在栅电极的一部分上方并与其接触，第二接触插塞包括第一导电材料。 接触材料层设置在有源区域中，接触材料层设置在第一接触插塞下方并且包括第一导电材料。

公开(公告)号：US07892939B2

公开(公告)日：2011-02-22

申请号：US12043384

申请日：2008-03-06

Applicant: Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

Inventor： Roland Hampp ,  Manfred Eller ,  Jin-Ping Han ,  Matthias Lipinski

IPC: H01L21/76 ,  H01L21/311

CPC classification number: H01L21/76262 ,  H01L21/76278

Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.

Abstract translation: 公开了STI模型中的有源面积损耗的防止，这导致根据工艺流程制造的器件中的器件性能提高。 多个不同实施例中通常共享的方法将当前常规STI结构转换为绝缘体用锥形图案化的工艺流程。 在锥形沟槽中的绝缘体的表面下方形成偏析层。 然后用半导体材料填充锥形沟槽，半导体材料被进一步处理以产生多个有源器件。 因此，有源器件是在图案化电介质中产生的，而不是在有源器件的半导体衬底中产生的STI。

公开(公告)号：US20100308418A1

公开(公告)日：2010-12-09

申请号：US12481373

申请日：2009-06-09

Applicant: Knut Stahrenberg ,  Roland Hampp ,  Jin-Ping Han ,  Klaus von Arnim

Inventor： Knut Stahrenberg ,  Roland Hampp ,  Jin-Ping Han ,  Klaus von Arnim

IPC: H01L27/088 ,  H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a gate dielectric and a cap layer disposed over the gate dielectric. The first transistor includes a gate including a metal layer disposed over the cap layer and a semiconductive material disposed over the metal layer. The semiconductor device includes a second transistor in a second region of the workpiece, which includes the gate dielectric and the cap layer disposed over the gate dielectric. The second transistor includes a gate that includes the metal layer disposed over the cap layer and the semiconductive material disposed over the metal layer. A thickness of the metal layer, a thickness of the semiconductive material, an implantation region of a channel region, or a doped region of the gate dielectric of the first transistor achieves a predetermined threshold voltage for the first transistor.

Abstract translation: 公开了半导体器件及其制造方法。 在一个实施例中，半导体器件包括具有栅极电介质的第一晶体管和设置在栅极电介质上的覆盖层。 第一晶体管包括包括设置在盖层上的金属层的栅极和设置在金属层上的半导体材料。 半导体器件包括在工件的第二区域中的第二晶体管，其包括设置在栅极电介质上的栅极电介质和盖层。 第二晶体管包括栅极，其包括设置在覆盖层上的金属层和设置在金属层上的半导体材料。 第一晶体管的金属层的厚度，半导体材料的厚度，沟道区的注入区域或栅极电介质的掺杂区域实现了第一晶体管的预定阈值电压。

公开(公告)号：US20100190328A1

公开(公告)日：2010-07-29

申请号：US12754294

申请日：2010-04-05

Applicant: Roland Hampp

Inventor： Roland Hampp

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

Abstract translation: 公开了形成自对准硅化物触点的结构和方法。 该结构包括设置在有源区上的栅电极，设置在栅极上的衬垫和有源区的至少一部分，设置在衬垫上的绝缘层。 第一接触插塞设置在绝缘层和衬垫中，第一接触插头设置在有源区域的一部分上方并与其接触，第一接触插塞包括第一导电材料。 第二接触插塞设置在绝缘层和衬垫中，第二接触插塞设置在栅电极的一部分上方并与其接触，第二接触插塞包括第一导电材料。 接触材料层设置在有源区域中，接触材料层设置在第一接触插塞下方并且包括第一导电材料。

公开(公告)号：US20100148262A1

公开(公告)日：2010-06-17

申请号：US12336702

申请日：2008-12-17

Applicant: Knut Stahrenberg ,  Karl-Heinz Bach ,  Manfred Eller ,  Roland Hampp ,  Jin-Ping Han ,  O Sung Kwon

Inventor： Knut Stahrenberg ,  Karl-Heinz Bach ,  Manfred Eller ,  Roland Hampp ,  Jin-Ping Han ,  O Sung Kwon

IPC: H01L29/772 ,  H01L21/02

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: Resistors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a semiconductive material over a workpiece, and patterning at least the semiconductive material, forming a gate of a transistor in a first region of the workpiece and forming a resistor in a second region of the workpiece. At least one substance is implanted into the semiconductive material of the gate of the transistor or the resistor so that the semiconductive material is different for the gate of the transistor and the resistor.

Abstract translation: 公开了电阻器，半导体器件及其制造方法。 在一个实施例中，制造电阻器的方法包括在工件上形成半导体材料，并且至少构图半导体材料，在工件的第一区域中形成晶体管的栅极，并在第二区域中形成电阻器 工件。 将至少一种物质注入到晶体管或电阻器的栅极的半导体材料中，使得半导体材料对于晶体管和电阻器的栅极是不同的。

公开(公告)号：US20090283852A1

公开(公告)日：2009-11-19

申请号：US12122849

申请日：2008-05-19

Applicant: Alois Gutmann ,  Roland Hampp ,  Scott Jansen

Inventor： Alois Gutmann ,  Roland Hampp ,  Scott Jansen

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/7846 ,  H01L21/76232 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/12 ,  H01L29/78 ,  H01L29/7848

Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

Abstract translation: 公开了应力诱导结构，方法和材料。 在一个实施例中，隔离区域包括在工件中形成的沟槽的下部中的绝缘材料和设置在绝缘材料上方的沟槽顶部的应力诱导材料。

公开(公告)号：US20070249128A1

公开(公告)日：2007-10-25

申请号：US11379285

申请日：2006-04-19

Applicant: Junjung Kim ,  JaeEon Park ,  Johnny Widodo ,  Andre Schenk ,  Alois Gutmann ,  Roland Hampp

Inventor： Junjung Kim ,  JaeEon Park ,  Johnny Widodo ,  Andre Schenk ,  Alois Gutmann ,  Roland Hampp

IPC: H01L21/473

CPC classification number: H01L21/76825 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02277 ,  H01L21/3105 ,  H01L21/31612

Abstract: Dielectric layers are formed on a substrate by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O3-TEOS) to form a layer of O3-TEOS on the substrate, and treating the layer of O3-TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the O3-TEOS layer by reducing the amount of water in the layer. Moreover, the UV treatment may also reduce the amount of silanol in the O3-TEOS layer, which can also increase reliability of the device.

Abstract translation: 通过执行臭氧四乙氧基硅烷（O 3 3 -TEOS）的低气压化学气相沉积（SACVD）在基底上形成介电层，以形成一层O 3 3 -TEOS 底物，并用紫外线（UV）辐射处理O 3 -TEOS层。 UV辐射处理可以通过减少层中的水的量来增加O 3/3层的拉伸应力。 此外，紫外线处理也可以减少O 3 3 -TEOS层中的硅烷醇的量，这也可以提高装置的可靠性。