公开(公告)号：US11789168B2

公开(公告)日：2023-10-17

申请号：US17408679

申请日：2021-08-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gilles Gasiot ,  Fady Abouzeid

IPC: G01T1/24 ,  H01L27/07 ,  H01L31/103

CPC classification number: G01T1/248 ,  G01T1/247 ,  H01L27/0761 ,  H01L31/103

Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

公开(公告)号：US20230329008A1

公开(公告)日：2023-10-12

申请号：US18335940

申请日：2023-06-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy BERTHELON ,  Olivier WEBER

IPC: H10B63/00

CPC classification number: H10B63/32 ,  H10B63/80

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

公开(公告)号：US11784275B2

公开(公告)日：2023-10-10

申请号：US17308651

申请日：2021-05-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles Baudot ,  Sebastien Cremer ,  Nathalie Vulliet ,  Denis Pellissier-Tanon

IPC: H01L33/00 ,  H01L31/105 ,  H01L31/0232 ,  G02B6/12 ,  H01L31/028

CPC classification number: H01L31/105 ,  G02B6/12004 ,  H01L31/028 ,  H01L31/02327

Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.

公开(公告)号：US20230317748A1

公开(公告)日：2023-10-05

申请号：US18129993

申请日：2023-04-03

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Jonathan STECKEL ,  Emmanuel JOSSE ,  Eric MAZALEYRAT ,  Youness RADID

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14627 ,  H01L27/14612 ,  H01L27/14636

Abstract: An imaging device includes an array of photosensors. A film of semiconductor nanoparticles is common to the photosensors of the array. The nanoparticles are configured to be excited by light with wavelengths in a range from 280 to 1500 nanometers. Each photosensor includes a top electrode and a bottom electrode positioned on opposite sides of the film of semiconductor nanoparticles. At least some of the photosensors further include a filter configured to transmit light with wavelengths in a range from 280 to 400 nanometers, and to at least partially filter out light with wavelengths greater than 400 nanometers from reaching the photosensor. A transistor level is electrically coupled to the top and bottom electrodes of the photosensors.

公开(公告)号：US20230290801A1

公开(公告)日：2023-09-14

申请号：US18198384

申请日：2023-05-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14603 ,  H01L27/14616

Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

公开(公告)号：US20230260574A1

公开(公告)日：2023-08-17

申请号：US17673550

申请日：2022-02-16

Applicant: Universite D'Aix Marseille ,  Centre National De La Recherche Scientifique ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Jean-Michel PORTAL ,  Vincenzo DELLA MARCA ,  Jean-Pierre WALDER ,  Julien GASQUEZ ,  Philippe BOIVIN

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/72 ,  G11C2013/0054

Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.

公开(公告)号：US20230258866A1

公开(公告)日：2023-08-17

申请号：US18152435

申请日：2023-01-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Houssein El Dirani

IPC: G02B6/136 ,  G02B6/132

CPC classification number: G02B6/136 ,  G02B6/132 ,  G02B2006/12061

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor device includes forming a first front layer and a first rear layer of a first material respectively on a front main face and a rear main face of a semiconductor substrate wafer; forming a first plurality of trenches and a second plurality of trenches respectively in a surface of the first front layer and in a surface of the first rear layer; forming a second front layer of a second material on the first front layer, where the second front layer extends over the first front layer, in the first plurality of trenches, and between the first plurality of trenches on the surface of the first front layer; and forming a second rear layer of the second material on the surface of the first rear layer, wherein the second rear layer extends over the first rear layer, in the second plurality of trenches, and between the second plurality of trenches on the surface of the first rear layer.

公开(公告)号：US20230074527A1

公开(公告)日：2023-03-09

申请号：US17988141

申请日：2022-11-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Cremer

IPC: G02F1/1333 ,  G02B6/13 ,  G02F1/01

Abstract: A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.

公开(公告)号：US20230068198A1

公开(公告)日：2023-03-02

申请号：US17890113

申请日：2022-08-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Simon Guillaumet ,  Benjamin Vianne ,  Stephane Zoll

IPC: G02B5/02

Abstract: The present description concerns an optical diffuser including a first layer having an electrically-conductive track formed therein, and a second layer, having the first layer resting thereon resting thereon, and having at least two electrically-conductive pillars extending across the entire thickness of the second layer formed therein. The second layer includes at least one first region located under the conductive track comprising no pillar.

公开(公告)号：US11581449B2

公开(公告)日：2023-02-14

申请号：US16703689

申请日：2019-12-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Younes Benhammou ,  Dominique Golanski ,  Denis Rideau

IPC: H01L31/107 ,  H01L31/028 ,  H01L31/0745 ,  H01L31/18

Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.