公开(公告)号：US12059299B2

公开(公告)日：2024-08-13

申请号：US17567507

申请日：2022-01-03

Applicant: Socionext Inc.

Inventor： Naoto Adachi ,  Hiroshi Kishi ,  Hiroaki Takagi

IPC: A61B8/00

CPC classification number: A61B8/4472 ,  A61B8/54 ,  A61B8/565

Abstract: An ultrasonic probe includes a wireless transmitter-receiver configured to perform communication through a wireless network having a plurality of channels and obtain identification information of apparatuses connected to the wireless network from the apparatuses; a memory configured to store identification information for identifying other ultrasonic probes from among the apparatuses; and a processor configured to count other ultrasonic probes connected with the wireless network on a per channel basis with respect to the plurality of channels based on the identification information obtained by the wireless transmitter-receiver and the identification information stored in the memory, and determine to connect to a channel at which the number of the other ultrasonic probes counted by the processor is smallest.

公开(公告)号：US20240256053A1

公开(公告)日：2024-08-01

申请号：US18629153

申请日：2024-04-08

Applicant: Socionext Inc.

Inventor： Yuji KUWAHARA ,  Daiki CHO

IPC: G06F3/01 ,  G01S13/06 ,  G01S13/50

CPC classification number: G06F3/017 ,  G01S13/06 ,  G01S13/50

Abstract: A signal processing method is executed by a signal processing device connected to a radio device that transmits radio waves in given periods and receives reflection waves, to process signals of the reflection waves. The signal processing method includes: obtaining positional information on a moving object at respective times based on the signals of the reflection waves; identifying a coordinate that is a coordinate in an axis in a transmission direction of the radio waves, and satisfies an end condition of a gesture from among the obtained positional information at the respective times; and extracting a group of consecutive coordinates including the identified coordinate as an end point.

公开(公告)号：US12046598B2

公开(公告)日：2024-07-23

申请号：US17507567

申请日：2021-10-21

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L23/5286 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

公开(公告)号：US20240234322A1

公开(公告)日：2024-07-11

申请号：US18609760

申请日：2024-03-19

Applicant: Socionext Inc.

Inventor： Hayato SHINOHARA

IPC: H01L23/528 ,  H01L27/118

CPC classification number: H01L23/5286 ,  H01L27/11803

Abstract: In a semiconductor integrated circuit device, a plurality of standard cells arranged in an X direction include a first standard cell having a logical function and including a transistor having a channel portion extending in the X direction, and a second standard cell including a signal line placed to extend in the X direction. The signal line is formed in a buried interconnect layer, and has an overlap with the channel portion at a position in a Y direction.

公开(公告)号：US20240224492A1

公开(公告)日：2024-07-04

申请号：US18606421

申请日：2024-03-15

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Wenzhen WANG ,  Hirotaka TAKENO

IPC: H10B10/00

CPC classification number: H10B10/18

Abstract: A semiconductor device includes first and second power supply lines and first and second ground lines provided on a first surface of a substrate, and third and fourth power supply lines provided on a second surface of the substrate. The second power supply line and the third power supply line are connected through vias provided in the substrate. The semiconductor device includes first and second areas arranged to have a third area sandwiched in-between, and a power switch circuit including switch transistors connected between the third and fourth power supply lines.

公开(公告)号：US12028088B2

公开(公告)日：2024-07-02

申请号：US17850235

申请日：2022-06-27

Applicant: Socionext Inc.

Inventor： Jayaraman Kumar ,  Kenneth Stephen Hunt

IPC: H03M1/38 ,  H03M1/06 ,  H03M1/18 ,  H03M1/46

CPC classification number: H03M1/38 ,  H03M1/0697 ,  H03M1/183 ,  H03M1/462 ,  H03M1/468

Abstract: Analogue-to-digital converter, ADC, circuitry, including: an analogue input terminal; a comparator having first and second comparator-input terminals; and successive-approximation control circuitry to apply a potential difference across the first and second comparator-input terminals based on an input voltage signal, and to control the potential difference for a series of successive approximation operations to cause the comparator to test in each successive approximation operation whether a magnitude of an analogue input voltage signal is larger or smaller than a corresponding test value, the test value for each successive approximation operation being, dependent on a comparison result generated by the comparator in the preceding approximation operation, bigger or smaller than the test value for the preceding approximation operation by a difference amount configured for that successive approximation operation.

公开(公告)号：US20240213300A1

公开(公告)日：2024-06-27

申请号：US18598870

申请日：2024-03-07

Applicant: Socionext Inc.

Inventor： Isaya SOBUE ,  Hideyuki KOMURO

IPC: H01L27/092 ,  H01L27/06 ,  H01L23/528

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L23/5286 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.

公开(公告)号：US20240194543A1

公开(公告)日：2024-06-13

申请号：US18442973

申请日：2024-02-15

Applicant: Socionext Inc.

Inventor： Kosuke KUSUMI

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor device includes a substrate; and a plurality of semiconductor elements each including a first terminal and a second terminal connected to the substrate, and an internal wiring connecting the first terminal and the second terminal to each other. A wiring path is provided to sequentially connect the plurality of semiconductor elements, by connecting the first terminal of each of the plurality of semiconductor elements to the second terminal of another one of the plurality of semiconductor elements via a substrate wiring provided in the substrate. One of the plurality of semiconductor elements includes a determination circuit provided on a path of the internal wiring. The determination circuit is configured to transmit a determination signal to the first terminal, and determine an abnormality of the wiring path based on the determination signal received by the second terminal via the wiring path.

公开(公告)号：US11990464B2

公开(公告)日：2024-05-21

申请号：US17204797

申请日：2021-03-17

Applicant: SOCIONEXT INC.

Inventor： Toru Matsui

IPC: H01L27/02 ,  H01L27/11 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11898 ,  H01L2224/0613 ,  H01L2224/06134 ,  H01L2224/0616 ,  H01L2224/06163 ,  H01L2224/06177

Abstract: Provided is a semiconductor integrated circuit device including a plurality of columns of IO cells and having a configuration capable of reducing wiring delays without causing an increase in the area. The semiconductor integrated circuit device includes a first IO cell column group including an IO cell column closest to a periphery of a chip, and a second IO cell column group including an IO cell column adjacent to the first IO cell column group at the side closer to the core region. At least one of the first IO cell column group or the second IO cell column group includes two or more IO cell columns, and the two or more IO cell columns are aligned in the second direction such that the lower power supply voltage regions face each other or the higher power supply voltage regions face each other.

公开(公告)号：US20240153549A1

公开(公告)日：2024-05-09

申请号：US18413959

申请日：2024-01-16

Applicant: Socionext Inc.

Inventor： Masanobu HIROSE

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H10B10/12 ,  H10B10/125

Abstract: Transistors (N1 to N12) corresponding to drive transistors (PD1, PD2), access transistors (PG1, PG2), read drive transistor (RPD1), and read access transistor (RPG1) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. The transistors (P1, P2) overlap the transistors (N3, N8), respectively, in plan view.