公开(公告)号：US20120110229A1

公开(公告)日：2012-05-03

申请号：US13349210

申请日：2012-01-12

Applicant: Steven C. Woo ,  Scott C. Best

Inventor： Steven C. Woo ,  Scott C. Best

IPC: G06F13/42

CPC classification number: E04B2/58 ,  E04B1/24 ,  E04C2/423 ,  G06F13/4243

Abstract: A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract translation: 存储器总线，其具有耦合到存储器控制器的第一总线段，存储器控制器包括控制逻辑和第一存储器件，耦合到第二存储器件的第二总线段以及第一总线段和第二总线段之间的开关。 控制逻辑将控制信息输出到开关以选择性地分离第一总线段和第二总线段以实现存储器总线的长度的改变，以使得能够以第一数据速率相对于第一存储器件的数据传输。 另外，控制逻辑可以将控制信息输出到开关以选择性地耦合第一总线段和第二总线段以增加存储器总线的长度，以使得能够以第二数据速率相对于第二存储器设备进行数据传输， 比第一个数据速率慢。

公开(公告)号：US20090323386A1

公开(公告)日：2009-12-31

申请号：US12557361

申请日：2009-09-10

Applicant: Steven C. Woo ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Craig E. Hampel

IPC: G11C5/02 ,  G11C5/14

CPC classification number: G11C5/02

Abstract: The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus.

Abstract translation: 内存模块包括前面和后面。 在每个面上设置多个装置。 第一控制线串联连接前面和后表面上的第一组设备，使得第一组设备通常向数据总线贡献多个位。 第二控制线串联连接前面和后表面上的第二组设备，使得第二组设备通常向数据总线贡献多个位。

公开(公告)号：US06373768B1

公开(公告)日：2002-04-16

申请号：US09401988

申请日：1999-09-23

Applicant: Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

IPC: G11C704

Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory module having a plurality of memory devices coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature (actual or estimated) of the memory device. Based on the determined operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

公开(公告)号：US5422983A

公开(公告)日：1995-06-06

申请号：US93795

申请日：1993-07-19

Applicant: Patrick F. Castelaz ,  Dwight E. Mills ,  Steven C. Woo ,  Jack I. Jmaev ,  Tammy L. Henrikson

Inventor： Patrick F. Castelaz ,  Dwight E. Mills ,  Steven C. Woo ,  Jack I. Jmaev ,  Tammy L. Henrikson

IPC: G06N3/063 ,  G06F15/18

CPC classification number: G06N3/063

Abstract: The neural engine (20) is a hardware implementation of a neural network for use in real-time systems. The neural engine (20) includes a control circuit (26) and one or more multiply/accumulate circuits (28). Each multiply/accumulate circuit (28) includes a parallel/serial arrangement of multiple multiplier/accumulators (84) interconnected with weight storage elements (80) to yield multiple neural weightings and sums in a single clock cycle. A neural processing language is used to program the neural engine (20) through a conventional host personal computer (22). The parallel processing permits very high processing speeds to permit real-time pattern classification capability.

Abstract translation: 神经引擎（20）是用于实时系统的神经网络的硬件实现。 神经发动机（20）包括控制电路（26）和一个或多个乘法/累加电路（28）。 每个乘法/累加电路（28）包括与重量存储元件（80）互连的多个乘法器/累加器（84）的并行/串行布置，以在单个时钟周期内产生多个神经权重和求和。 神经处理语言用于通过常规主机个人计算机（22）对神经发动机（20）进行编程。 并行处理允许非常高的处理速度以允许实时模式分类能力。

公开(公告)号：US07370152B2

公开(公告)日：2008-05-06

申请号：US10881413

申请日：2004-06-29

Applicant: Steven C. Woo ,  Bradley A. May ,  Liewei Bao

Inventor： Steven C. Woo ,  Bradley A. May ,  Liewei Bao

IPC: G06F12/00

CPC classification number: G06F13/1642 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodiments, results of a prefetching operations are stored in a prefetch buffer configured to provide an automatic aging mechanism, which evicts prefetched data from time to time. The prefetched data in the prefetch buffer is released and sent back to the requester in order with respect to previous memory access requests.

Abstract translation: 如果存储器控制器在一段活动之后检测到存储器系统空闲，或者如果发生预取缓冲器读取命中，则存储器控制器监视来自一个或多个计算机子系统的请求并发出一个或多个预取命令。 在一些实施例中，预取操作的结果被存储在预取缓冲器中，该预取缓冲器被配置为提供自动老化机制，其不时地推移预取的数据。 预取缓冲器中的预取数据被释放，并相对于先前的存储器访问请求被发送回请求者。

公开(公告)号：US07003639B2

公开(公告)日：2006-02-21

申请号：US10873670

申请日：2004-06-21

Applicant: Ely K. Tsern ,  Ramprasad Satagopan ,  Richard M. Barth ,  Steven C. Woo

Inventor： Ely K. Tsern ,  Ramprasad Satagopan ,  Richard M. Barth ,  Steven C. Woo

IPC: G06F12/00

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  G06F12/0215 ,  G06F2212/1028 ,  G11C11/4074 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.

公开(公告)号：US06349050B1

公开(公告)日：2002-02-19

申请号：US09686744

申请日：2000-10-10

Applicant: Steven C. Woo ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Craig E. Hampel

IPC: G11C502

CPC classification number: G11C5/02

Abstract: Systems and methods for reducing heat flux in memory systems are described. In various embodiments, heat flux reductions are achieved by manipulating the device IDs of individual memory devices that comprise a memory module. Through the various described techniques, the per-face heat flux can be desirably reduced. Further, in some embodiments, reductions in heat flux are achieved by providing control lines that operably connect memory devices on different faces of a memory module.

Abstract translation: 描述了用于减少存储器系统中的热通量的系统和方法。 在各种实施例中，通过操纵包括存储器模块的各个存储器件的器件ID来实现热通量减少。 通过各种描述的技术，可以期望地减少每面热通量。 此外，在一些实施例中，通过提供可操作地连接存储器模块的不同面上的存储器件的控制线来实现热通量的减少。

公开(公告)号：US20110317465A1

公开(公告)日：2011-12-29

申请号：US13224251

申请日：2011-09-01

Applicant: Steven C. Woo ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Craig E. Hampel

IPC: G11C5/06

CPC classification number: G11C5/02

Abstract: The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus.

Abstract translation: 内存模块包括前面和后面。 在每个面上设置多个装置。 第一控制线串联连接前面和后表面上的第一组设备，使得第一组设备通常向数据总线贡献多个位。 第二控制线串联连接前面和后表面上的第二组设备，使得第二组设备通常向数据总线贡献多个位。

公开(公告)号：US20110289510A1

公开(公告)日：2011-11-24

申请号：US13143993

申请日：2010-02-02

Applicant: Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohuslav Rychlik

Inventor： Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohuslav Rychlik

IPC: G06F9/46

CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815

Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

Abstract translation: 缓存相干协议在共享内存空间的多个处理器（或处理器核心）之间分配原子操作。 当包括修改存储在共享存储器空间中的数据的指令的原子操作被引导到不具有与数据相关联的地址的控制的第一处理器时，第一处理器发送包括指令的请求 修改数据到第二个处理器。 然后，已经具有对地址的控制的第二处理器修改数据。 此外，第一处理器可以立即进行另一个指令，而不是等待地址变得可用。

公开(公告)号：US20110286267A1

公开(公告)日：2011-11-24

申请号：US13140345

申请日：2009-10-08

Applicant: Bohuslav Rychlik ,  John Eric Linstadt ,  Brent Steven Haukness ,  Steven C. Woo

Inventor： Bohuslav Rychlik ,  John Eric Linstadt ,  Brent Steven Haukness ,  Steven C. Woo

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628

Abstract: A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits.

Abstract translation: 一种操作存储器件的方法包括接收要存储在器件中的多级单元中的第一组和第二组位。 从用于存储多级单元中的第一和第二位组的多个多级编码中选择多级编码。 每个多级编码包括用于相应多级单元的至少四个编码电平。 相应的多级编码具有与根据相应的多级编码将第一和第二组位编程到多级单元中相关联的成本。 基于相应编码的相应成本来选择多级编码。 第一和第二组位根据所选择的多级编码进行编码，以产生用于存储在设备中的编码数据，使得相应的多级单元存储来自第一和第二组位的相应位。