Apparatus and method for optimizing loop buffer in reconfigurable processor
    22.
    发明申请
    Apparatus and method for optimizing loop buffer in reconfigurable processor 有权
    用于优化可重构处理器中循环缓冲器的装置和方法

    公开(公告)号:US20070150710A1

    公开(公告)日:2007-06-28

    申请号:US11525913

    申请日:2006-09-25

    IPC分类号: G06F9/44

    摘要: A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.

    摘要翻译: 一种可重配置处理器,包括用于存储用于至少一个环路配置的配置位的配置存储器; 用于存储指示循环中的操作是否为延迟操作的位信息的有效信息存储器; 以及至少一个处理单元,用于通过参考从有效信息存储器发送的比特信息来确定下一个周期中的操作是否是延迟操作,并且根据来自所述有用信息存储器的配置位选择性地执行改变和配置的实现 基于确定结果的配置存储器。

    Fused multiply-add apparatus and method
    23.
    发明授权
    Fused multiply-add apparatus and method 有权
    熔融多重加法装置及方法

    公开(公告)号:US08805915B2

    公开(公告)日:2014-08-12

    申请号:US13153885

    申请日:2011-06-06

    IPC分类号: G06F7/38

    CPC分类号: G06F7/483 G06F7/5443

    摘要: A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.

    摘要翻译: 提供固定的乘法(FMA)装置和方法。 该FMA装置包括:部分乘积发生器,被配置为产生部分和和部分进位;进位保存加法器,被配置为通过将部分和和相加来产生具有第一位大小的部分和和具有第一位大小的部分进位 部分进位到第三浮点数的尾数的最低有效位(LSB),进位选择加法器,被配置为通过将第一位大小部分和和第一位大小部分相加来生成具有第二位大小的尾数 携带到第三浮点数的最高有效位(MSB),以及选择器,被配置为根据是否将第一位大小部分和和第一位大小部分进位发送到进位存储加法器或进位选择加法器 第三个浮点数的尾数为零。

    Washbasin
    24.
    发明授权
    Washbasin 有权
    脸盆

    公开(公告)号:US08499375B2

    公开(公告)日:2013-08-06

    申请号:US13330613

    申请日:2011-12-19

    IPC分类号: A47K1/04

    CPC分类号: A47K1/04 F16L25/08

    摘要: A washbasin includes: a washbasin body having a water containing space and comprising an insertion hole formed in a front surface thereof in a downward inclined direction and a drain hole formed on the bottom surface thereof; a water supply nozzle projected toward the water containing space through the insertion hole from a rear end of the washbasin body, wherein the projected portion of the water supply nozzle is rotated in a direction desired by a user so as to control a water supply direction and a water supply amount; a cold/hot water supply valve buried in a one-side edge of the washbasin body and coupled to the water supply nozzle through a pipe; and a cold/hot selection level installed on the top surface of the cold/hot water supply valve and selectively supplying cold/hot water to the water supply nozzle.

    摘要翻译: 洗脸盆包括:具有含水空间的洗脸盆主体,具有形成在其前表面上的向下倾斜方向的插入孔和形成在其底面上的排水孔; 所述供水喷嘴从所述洗脸盆主体的后端经由所述插入孔朝向所述容纳空间突出,其中所述供水喷嘴的突出部分沿着使用者期望的方向旋转,以便控制供水方向,以及 供水量; 一个冷/热水供应阀,它埋在洗脸盆主体的一侧边缘,并通过管道与供水喷嘴相连; 以及冷/热选择级,安装在冷/热水供应阀的顶表面上并选择性地向供水喷嘴供应冷/热水。

    RECONFIGURABLE PROCESSOR AND MINI-CORE OF RECONFIGURABLE PROCESSOR
    25.
    发明申请
    RECONFIGURABLE PROCESSOR AND MINI-CORE OF RECONFIGURABLE PROCESSOR 有权
    可重构处理器和可重构处理器的微型核心

    公开(公告)号:US20130151815A1

    公开(公告)日:2013-06-13

    申请号:US13711418

    申请日:2012-12-11

    IPC分类号: G06F15/78

    摘要: A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.

    摘要翻译: 可重配置处理器包括多个微型核心和连接微型核心的外部网络。 每个微型核心包括包括第一组操作元件的第一功能单元,包括与第一组操作元件不同的第二组操作元件的第二功能单元,以及内部网络,第一功能单元 单元和第二个功能单元连接。

    MEMORY CONTROLLER AND MEMORY CONTROL METHOD
    26.
    发明申请
    MEMORY CONTROLLER AND MEMORY CONTROL METHOD 有权
    存储控制器和存储器控制方法

    公开(公告)号:US20130151794A1

    公开(公告)日:2013-06-13

    申请号:US13709542

    申请日:2012-12-10

    IPC分类号: G06F12/00

    摘要: Provided is a memory controller that manages memory access requests between the processor and the memory. In response to the memory controller receiving two or more memory access requests for the same area of memory, the memory controller is configured to stall the memory controller and sequentially process the memory access requests.

    摘要翻译: 提供了一种管理处理器和存储器之间的存储器访问请求的存储器控​​制器。 响应于存储器控制器接收到相同存储器区域的两个或多个存储器访问请求,存储器控制器被配置为停止存储器控制器并且顺序地处理存储器访问请求。

    PROCESSOR, APPARATUS AND METHOD FOR GENERATING INSTRUCTIONS
    27.
    发明申请
    PROCESSOR, APPARATUS AND METHOD FOR GENERATING INSTRUCTIONS 有权
    处理器,装置和产生指令的方法

    公开(公告)号:US20130145133A1

    公开(公告)日:2013-06-06

    申请号:US13690079

    申请日:2012-11-30

    IPC分类号: G06F9/30

    CPC分类号: G06F9/3004 G06F9/30043

    摘要: A processor, apparatus and method to use a multiple store instruction based on physical addresses of registers are provided. The processor is configured to execute an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating apparatus is configured to generate an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating method includes detecting a code area that instructs to store data of a plurality of registers in a memory, from a program code. The instruction generating method further includes generating an instruction corresponding to the code area by mapping physical addresses of the registers to a first area of the instruction.

    摘要翻译: 提供了一种基于寄存器的物理地址使用多存储指令的处理器,装置和方法。 处理器被配置为执行将多个寄存器的数据存储在存储器中的指令,该指令包括写入每个寄存器的物理地址的第一区域。 指令生成装置被配置为生成将多个寄存器的数据存储在存储器中的指令,该指令包括写入每个寄存器的物理地址的第一区域。 指令生成方法包括从程序代码检测指示将多个寄存器的数据存储在存储器中的代码区域。 指令生成方法还包括通过将寄存器的物理地址映射到指令的第一区域来生成与代码区域相对应的指令。

    COMPILING APPARATUS AND METHOD OF A MULTICORE DEVICE
    29.
    发明申请
    COMPILING APPARATUS AND METHOD OF A MULTICORE DEVICE 有权
    编码装置和多种装置的方法

    公开(公告)号:US20120159507A1

    公开(公告)日:2012-06-21

    申请号:US13116601

    申请日:2011-05-26

    IPC分类号: G06F9/50

    CPC分类号: G06F8/451 G06F9/5088

    摘要: An apparatus and method capable of reducing idle resources in a multicore device and improving the use of available resources in the multicore device are provided. The apparatus includes a static scheduling unit configured to generate one or more task groups, and to allocate the task groups to virtual cores by dividing or combining the tasks included in the task groups based on the execution time estimates of the task groups. The apparatus also includes a dynamic scheduling unit configured to map the virtual cores to physical cores.

    摘要翻译: 提供了一种能够减少多核设备中的空闲资源并改进多核设备中可用资源的使用的装置和方法。 该装置包括:静态调度单元,被配置为生成一个或多个任务组,并且通过基于任务组的执行时间估计来划分或组合包括在任务组中的任务来将任务组分配给虚拟核。 该装置还包括被配置为将虚拟核心映射到物理核心的动态调度单元。

    SEMICONDUCTOR DEVICE HAVING GUARD RING, DISPLAY DRIVER CIRCUIT, AND DISPLAY APPARATUS
    30.
    发明申请
    SEMICONDUCTOR DEVICE HAVING GUARD RING, DISPLAY DRIVER CIRCUIT, AND DISPLAY APPARATUS 审中-公开
    具有保护环,显示驱动电路和显示设备的半导体器件

    公开(公告)号:US20110199346A1

    公开(公告)日:2011-08-18

    申请号:US13025754

    申请日:2011-02-11

    CPC分类号: H01L21/761 H01L27/0251

    摘要: A semiconductor device includes a semiconductor substrate having a first conductivity type, at least two first well regions which have a second conductivity type and a predetermined depth in the semiconductor substrate, at least one second well region which has the first conductivity type and a predetermined depth in each of the first well regions, and a guard-ring region which has the second conductivity type and a predetermined depth and is positioned between the first well regions to be separated by a predetermined distance from the first well regions. The guard-ring region is connected to a ground voltage.

    摘要翻译: 半导体器件包括具有第一导电类型的半导体衬底,在半导体衬底中具有第二导电类型和预定深度的至少两个第一阱区,具有第一导电类型和预定深度的至少一个第二阱区 以及具有第二导电类型和预定深度并且位于第一阱区之间以与第一阱区隔开预定距离的保护环区域。 保护环区域连接到接地电压。