Nonvolatile memory devices and methods of fabricating the same
    21.
    发明申请
    Nonvolatile memory devices and methods of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号:US20080025096A1

    公开(公告)日:2008-01-31

    申请号:US11704205

    申请日:2007-02-09

    Abstract: A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.

    Abstract translation: 非易失性存储器件包括多个第一控制栅电极,第二控制栅电极,第一存储节点膜和第二存储节点膜。 第一控制栅电极凹入半导体衬底。 每个第二控制栅电极设置在两个相邻的第一控制栅极之间。 第二控制栅电极设置在第一控制栅电极上的半导体衬底上。 第一存储节点膜设置在半导体衬底和第一控制栅电极之间。 第二存储节点膜设置在半导体衬底和第二控制栅电极之间。 一种制造非易失性存储器件的方法包括形成第一存储节点膜,形成第一控制栅电极,形成第二存储节点膜,以及形成第二控制栅电极。

    Non-volatile memory device having four storage node films and methods of operating and manufacturing the same
    22.
    发明申请
    Non-volatile memory device having four storage node films and methods of operating and manufacturing the same 审中-公开
    具有四个存储节点膜的非易失性存储器件及其操作和制造方法

    公开(公告)号:US20070296033A1

    公开(公告)日:2007-12-27

    申请号:US11704363

    申请日:2007-02-09

    CPC classification number: H01L29/7887 H01L29/42332 H01L29/7851 H01L29/7923

    Abstract: A nonvolatile memory device that may operate in a multi-bit mode and a method of operating and manufacturing the nonvolatile memory device are provided. The nonvolatile memory device may include a first source region and a first drain region that are respectively in first fin portions on both sides of a control gate electrode and respectively separated from the control gate electrode, a second source region and a second drain region that are respectively formed in second fin portions on both sides of the control gate electrode and respectively separated from the control gate electrode, first and second storage node layers that are formed with the control gate electrode therebetween and on the side of the first fin opposite to a buried insulating layer between first and second fins, and third and fourth storage node layers that are formed with the control gate electrode therebetween and on the side of the second fin opposite to the buried insulating layer. The nonvolatile memory device may further include a semiconductor substrate including the first and second fins, a control gate electrode on the sides of the first and second fins opposite to the buried insulating layer and extending onto the buried insulating layer and a gate insulating layer between the first and second fins and the control gate electrode.

    Abstract translation: 提供了可以以多位模式操作的非易失性存储器件以及操作和制造非易失性存储器件的方法。 非易失性存储器件可以包括第一源极区域和第一漏极区域,其分别位于控制栅极电极的两侧的第一鳍片部分中,并且分别与控制栅极电极,第二源极区域和第二漏极区域分离 分别形成在控制栅电极的两侧的第二鳍部分中,并分别与控制栅电极分离,第一和第二存储节点层在其间形成有控制栅极电极,并且在第一鳍片的与掩埋 在第一和第二散热片之间的绝缘层,以及在其间形成有控制栅极电极的第三和第四存储节点层,以及在第二鳍片与掩埋绝缘层相对的一侧。 非易失性存储器件还可以包括:包括第一和第二鳍片的半导体衬底;在第一和第二鳍片的与掩埋绝缘层相对并且延伸到掩埋绝缘层上的侧面上的控制栅极电极和位于掩模绝缘层之间的栅极绝缘层 第一和第二鳍片和控制栅电极。

    NAND-type nonvolatile memory devices having common bit lines and methods of operating the same
    24.
    发明申请
    NAND-type nonvolatile memory devices having common bit lines and methods of operating the same 审中-公开
    具有公共位线的NAND型非易失性存储器件及其操作方法

    公开(公告)号:US20070183204A1

    公开(公告)日:2007-08-09

    申请号:US11657652

    申请日:2007-01-25

    CPC classification number: G11C16/0483 G11C7/18

    Abstract: A NAND-type nonvolatile memory device includes a first string and a second string. The ends of each of the first and second strings are connected to a common bit line and a common source line, respectively. Each of the first string and the second string have a string selection transistors, a plurality of unit devices and a source selection transistor. Word lines are respectively connected to control gates of the unit devices in the same rows. A first string selection line and a second string selection line are respectively connected to the gates of the string selection transistors of the first string and the second string. A first source selection line and a second source selection line are respectively connected to the gates of the first string and the second string.

    Abstract translation: NAND型非易失性存储器件包括第一串和第二串。 第一和第二串中的每一个的端部分别连接到公共位线和公共源极线。 第一串和第二串中的每一个具有串选择晶体管,多个单元器件和源极选择晶体管。 字线分别连接到相同行中的单元设备的控制栅极。 第一串选择线和第二串选择线分别连接到第一串和第二串的串选择晶体管的栅极。 第一源选择线和第二源选择线分别连接到第一串和第二串的栅极。

    Fin-FET having GAA structure and methods of fabricating the same
    25.
    发明申请
    Fin-FET having GAA structure and methods of fabricating the same 有权
    具有GAA结构的Fin-FET及其制造方法

    公开(公告)号:US20070145431A1

    公开(公告)日:2007-06-28

    申请号:US11505936

    申请日:2006-08-18

    CPC classification number: H01L29/785 H01L29/42392 H01L29/66795

    Abstract: Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.

    Abstract translation: 本发明的示例性实施例涉及一种半导体器件及其制造方法。 本发明的其它示例性实施例涉及一种具有鳍型沟道区的鳍式场效应晶体管(Fin-FET)及其制造方法。 提供了可以使用围绕鳍片的整个区域作为沟道区域的具有栅极全(GAA)结构的鳍FET。 具有GAA结构的Fin-FET包括具有主体,一对支撑柱和鳍的半导体衬底。 一对支柱可能从身体突出。 翅片可以与主体间隔开,并且可以具有连接到一对支撑柱并由其支撑的端部。 栅电极可围绕半导体衬底的鳍的至少一部分。 栅电极可以与半导体衬底绝缘。 栅极绝缘层可以插入在半导体衬底的栅电极和鳍之间。

    Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions
    26.
    发明申请
    Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
    制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法

    公开(公告)号:US20070048934A1

    公开(公告)日:2007-03-01

    申请号:US11505335

    申请日:2006-08-17

    Abstract: Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

    Abstract translation: 提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法,显示出与SOI结构相关的一些特征优点,提供增加的工作电流和/或降低的接触电阻。 制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域,从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。 在形成翅片之后,形成第三绝缘膜以填充第二沟槽并支撑翅片。 然后去除第一绝缘膜的一部分以打开翅片之间的空间,其中可以形成包括栅极电介质,栅电极和附加接触,绝缘和存储节点结构的附加结构。

    Off-axis projection optical system and extreme ultraviolet lithography apparatus using the same
    27.
    发明申请
    Off-axis projection optical system and extreme ultraviolet lithography apparatus using the same 有权
    离轴投影光学系统和使用其的极紫外光刻设备

    公开(公告)号:US20060284113A1

    公开(公告)日:2006-12-21

    申请号:US11453775

    申请日:2006-06-16

    CPC classification number: G03F7/70241 G03F7/70941

    Abstract: An off-axis projection optical system including first and second mirrors that are off-axially arranged is provided. The tangential and sagittal radii of curvature of the first mirror may be R1t and R1s, respectively. The tangential and sagittal radii of curvature of the second mirror may be R2t and R2s, respectively. The incident angle of the beam from an object point to the first mirror 10 may be i1, and an incident angle of the beam reflected from the first mirror 10 to the second mirror 30 is i2. The values of R1t, R1s, R2t, R2s, i1 and i2 may satisfy the following Equation. R1t cos i1=R2t cos i2 R1s=R1t cos2i1 R2s=R2t cos2i2

    Abstract translation: 提供了一种离轴投影光学系统,其包括非轴向布置的第一和第二反射镜。 第一反射镜的切向和矢状曲率半径可以分别为R 1t 1和R 1s 1。 第二反射镜的切向和矢状曲率半径可以分别为R 2t 2和R 2s 3。 从物点到第一反射镜10的光束的入射角度可以为1&lt; 1&gt;,从第一反射镜10反射到第二反射镜30的光束的入射角为 2 。 R 1,R 1,R 2,R 2,R 2,R 1,R 2, SUB&gt;和i&lt; 2&gt;可以满足以下等式。 <?in-line-formula description =“In-line Formulas”end =“lead”?> R&lt; 1t&gt; cos&lt; 1&lt; 1&lt; 2&lt; > cos i <2> <?in-line-formula description =“In-line Formulas”end =“tail”?> <?in-line-formula description =“In-line Formulas”end = “引线”→R 1> = R 1t&lt; 2&gt;&lt; 2&lt;&lt; =“在线公式”end =“tail”?> <?in-line-formula description =“In-line Formulas”end =“lead”?> R <2> 2t 2 “in-line-formula description =”In-line Formulas“end =”tail“?>

    Mask for electromagnetic radiation and method of fabricating the same
    28.
    发明申请
    Mask for electromagnetic radiation and method of fabricating the same 审中-公开
    电磁辐射掩模及其制造方法

    公开(公告)号:US20060134531A1

    公开(公告)日:2006-06-22

    申请号:US11274474

    申请日:2005-11-16

    CPC classification number: G21K1/062 B82Y10/00 B82Y40/00 G03F1/24

    Abstract: A mask for lithography and a method of manufacturing the same. The mask may include a substrate, a reflection layer formed of a material capable of reflecting electromagnetic rays on the substrate and an absorption pattern formed in a desired pattern such that absorbing regions with respect to electromagnetic rays and windows through which electromagnetic rays pass are formed, wherein the absorption pattern includes at least one side surface that is adjacent to the window and is inclined with respect to the reflection layer. The method may include forming a reflection layer which is formed of a material capable of reflecting electromagnetic rays on a substrate, forming an absorption layer which is formed of a material capable of absorbing electromagnetic rays on the refection layer, and patterning the absorption layer to form an absorption pattern with at least one side surface adjacent to a window that has an inclined side surface with respect to the reflection layer.

    Abstract translation: 光刻用掩模及其制造方法。 掩模可以包括基板,由能够在基板上反射电磁射线的材料形成的反射层和形成为期望图案的吸收图案,使得形成相对于电磁射线通过的电磁射线和窗口的吸收区域, 其中所述吸收图案包括与所述窗口相邻并且相对于所述反射层倾斜的至少一个侧表面。 该方法可以包括形成由能够在基板上反射电磁射线的材料形成的反射层,形成由能够在反射层上吸收电磁射线的材料形成的吸收层,以及图案化吸收层以形成 具有与窗口相邻的至少一个侧表面的吸收图案,该窗口具有相对于反射层的倾斜侧表面。

    Method for preparing heteroepitaxial thin film
    30.
    发明授权
    Method for preparing heteroepitaxial thin film 失效
    异质外延薄膜的制备方法

    公开(公告)号:US06447605B1

    公开(公告)日:2002-09-10

    申请号:US09441968

    申请日:1999-11-17

    Abstract: Disclosed is a method for preparing heteroepitaxial thin films which are free of island structures which have a bad influence on the photoelectric properties and interfacial reactivity of the thin films. These heteroepitaxial thin films are deposited on grooved or curved surfaces of substrates. The use of grooved substrates relieves the coherent elastic strain from the thin films, thereby inhibiting the surface roughening and the island structure formation in the heteroepitaxial thin films. The method can be applied to all of the thin films that show island structures, including GaAs/Si and SiGe/Si typically used in semiconductor devices and various electronic parts, enabling the thin films to be flatly deposited at a significant thickness on various substrates without additionally processing.

    Abstract translation: 公开了一种制备异质外延薄膜的方法,该薄膜不含岛结构,对薄膜的光电特性和界面反应性有不良影响。 这些异质外延薄膜沉积在基板的凹槽或弯曲表面上。 使用带槽的衬底减轻了薄膜的相干弹性应变,从而抑制异质外延薄膜中的表面粗糙化和岛状结构的形成。 该方法可以应用于显示岛结构的所有薄膜,包括通常用于半导体器件中的GaAs / Si和SiGe / Si以及各种电子部件,使薄膜能够在各种基板上以显着的厚度平坦地沉积,而无需 额外处理。

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