公开(公告)号：US07893436B2

公开(公告)日：2011-02-22

申请号：US11932798

申请日：2007-10-31

Applicant: Yeon-Ju Kim ,  Chong-Chul Chai ,  Sung-Hoon Yang

Inventor： Yeon-Ju Kim ,  Chong-Chul Chai ,  Sung-Hoon Yang

IPC: H01L29/04

CPC classification number: G02F1/1345 ,  G02F1/136286 ,  G09G3/3611 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2320/0223 ,  H01L27/12 ,  H01L27/124

Abstract: An array substrate includes a base substrate which includes a display area and a peripheral area adjacent to the display area, a plurality of fan-out lines arranged in the peripheral area to receive a driving signal from an exterior source, at least one fan-out line among the plurality of fan-out lines arranged on a different layer from a layer on which remaining fan-out lines of the plurality of fan-out lines are arranged, a plurality of signal lines arranged in the display area to receive the driving signal from the plurality of fan-out lines and a pixel array arranged in the display area to receive the driving signal from the plurality of signal lines.

Abstract translation: 阵列基板包括基板，其包括显示区域和与显示区域相邻的周边区域，多个扇出线布置在外围区域中以从外部源接收驱动信号，至少一个扇出 布置在与布置有多个扇出线的剩余扇出线的层不同的多个扇出线中的多条信号线布置在显示区域中以接收驱动信号 从所述多个扇出线和布置在所述显示区域中的像素阵列接收来自所述多条信号线的驱动信号。

公开(公告)号：US20110001137A1

公开(公告)日：2011-01-06

申请号：US12780246

申请日：2010-05-14

Applicant: Kap-Soo YOON ,  Do-Hyun Kim ,  Sung-Hoon Yang ,  Ki-Hun Jeong ,  Jae-Ho Choi ,  Seung-Mi Seo

Inventor： Kap-Soo YOON ,  Do-Hyun Kim ,  Sung-Hoon Yang ,  Ki-Hun Jeong ,  Jae-Ho Choi ,  Seung-Mi Seo

IPC: H01L33/28 ,  H01L21/34

CPC classification number: H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/7869

Abstract: Provided is a thin-film transistor (TFT) display panel having improved electrical and reliability properties and a method of fabricating the TFT display panel. The TFT display panel includes gate wiring formed on a substrate; an oxide active layer pattern formed on the gate wiring; data wiring formed on the oxide active layer pattern to cross the gate wiring; a passivation layer formed on the oxide active layer pattern and the data wiring and made of nitrogen oxide; and a pixel electrode disposed on the passivation layer.

Abstract translation: 提供了具有改善的电气和可靠性的薄膜晶体管（TFT）显示面板和制造TFT显示面板的方法。 TFT显示面板包括形成在基板上的栅极布线; 形成在栅极布线上的氧化物有源层图案; 在所述氧化物有源层图案上形成的与所述栅极布线交叉的数据布线; 形成在氧化物活性层图案上的钝化层和由氮氧化物制成的数据布线; 以及设置在钝化层上的像素电极。

公开(公告)号：US07843538B2

公开(公告)日：2010-11-30

申请号：US11747014

申请日：2007-05-10

Applicant: Mee-Hye Jung ,  Ji-Won Sohn ,  Sung-Hoon Yang ,  Jin-Won Park ,  Seon-Ah Cho

Inventor： Mee-Hye Jung ,  Ji-Won Sohn ,  Sung-Hoon Yang ,  Jin-Won Park ,  Seon-Ah Cho

IPC: G02F1/1337

CPC classification number: G02F1/1343 ,  G02F1/133707 ,  G02F1/1393

Abstract: In a liquid crystal display device, the device includes a first substrate, a second substrate and a liquid crystal layer interposed therebetween. The first substrate includes a pixel electrode, a thin film transistor connected to the pixel electrode, and also a hitch to connect both a lower and upper electrode of the pixel electrode. The second substrate includes a common electrode having a lower domain division part and an upper domain division part, in which each of domain division part is formed at the position corresponding to the lower and upper electrode of the pixel electrode, respectively. Through the electric field controller connected at both sides of the upper electrode of the pixel electrode, quality of display image can improve without a darkening area occurring at one part of the unit pixel.

Abstract translation: 在液晶显示装置中，该装置包括第一基板，第二基板和插入其间的液晶层。 第一基板包括像素电极，连接到像素电极的薄膜晶体管，以及连接像素电极的下电极和上电极的连接。 第二基板包括具有下畴分割部分和上畴分割部分的公共电极，其中每个畴分割部分分别形成在与像素电极的下电极和上电极相对应的位置。 通过连接在像素电极的上部电极的两侧的电场控制器，可以改善显示图像的质量，而不会在单位像素的一部分处发生变暗区域。

公开(公告)号：US20100136775A1

公开(公告)日：2010-06-03

申请号：US12607567

申请日：2009-10-28

Applicant: Seung-Ha CHOI ,  Sang-Gab KIM ,  Bong-Kyu SHIN ,  Sang-Uk LIM ,  Jin-Ho JU ,  Sung-Hoon YANG ,  Sang-Woo WHANGBO ,  Jae-Ho CHOI ,  Ki-Yeup LEE ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Dong-Ju YANG ,  Hong-Kee CHIN ,  Yu-Gwang JEONG

Inventor： Seung-Ha CHOI ,  Sang-Gab KIM ,  Bong-Kyu SHIN ,  Sang-Uk LIM ,  Jin-Ho JU ,  Sung-Hoon YANG ,  Sang-Woo WHANGBO ,  Jae-Ho CHOI ,  Ki-Yeup LEE ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Dong-Ju YANG ,  Hong-Kee CHIN ,  Yu-Gwang JEONG

IPC: H01L21/28

CPC classification number: H01L29/4908 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/458 ,  H01L29/7869

Abstract: Provided is a method for manufacturing a thin-film transistor substrate, in which the etching characteristics of an insulating film and a passivation layer are enhanced. The insulating film and the passivation layer are deposited by low temperature chemical vapor deposition. The method includes disposing a gate wiring on an insulating substrate; disposing a gate insulating film on the gate wiring; disposing a data wiring on the gate insulating film; disposing a passivation layer on the data wiring; and forming a contact hole by etching at least one of the gate insulating film and the passivation layer, wherein at least one of the gate insulating film and the passivation layer is disposed at a temperature of about 280° C. or below, and the forming of the contact hole is performed at a pressure of about 60 mT or below.

Abstract translation: 提供一种制造薄膜晶体管基板的方法，其中提高了绝缘膜和钝化层的蚀刻特性。 通过低温化学气相沉积沉积绝缘膜和钝化层。 该方法包括在绝缘基板上设置栅极布线; 在栅极布线上设置栅极绝缘膜; 在栅极绝缘膜上设置数据布线; 在数据线上设置钝化层; 以及通过蚀刻所述栅极绝缘膜和所述钝化层中的至少一个来形成接触孔，其中所述栅极绝缘膜和所述钝化层中的至少一个设置在约280℃或更低的温度下，并且所述形成 的接触孔在约60mT以下的压力下进行。

公开(公告)号：US20100025690A1

公开(公告)日：2010-02-04

申请号：US12366178

申请日：2009-02-05

Applicant: Yeon-Ju KIM ,  Sung-Hoon Yang ,  So-Woon Kim ,  So-Hyun Lee

Inventor： Yeon-Ju KIM ,  Sung-Hoon Yang ,  So-Woon Kim ,  So-Hyun Lee

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L27/124 ,  G02F1/1345

Abstract: A thin film transistor substrate includes an insulating plate, a plurality of fan-out lines arranged on the insulating plate and including at least a pair of adjacent fan-out lines, a plurality of signal lines connected to the plurality of fan-out lines, and a plurality of thin film transistors connected to the plurality of signal lines. The adjacent fan-out lines partially overlap with each other, and each overlapping area of the adjacent fan-out lines is the same.

Abstract translation: 薄膜晶体管基板包括绝缘板，布置在绝缘板上的多个扇出线，并且至少包括一对相邻的扇出线，连接到多个扇出线的多条信号线， 以及连接到所述多条信号线的多个薄膜晶体管。 相邻的扇出线部分地彼此重叠，并且相邻扇出线的每个重叠区域是相同的。

公开(公告)号：US20090185126A1

公开(公告)日：2009-07-23

申请号：US12332249

申请日：2008-12-10

Applicant: Sung Ryul Kim ,  Yong-Mo Choi ,  Sung-Hoon Yang ,  Hwa-Yeul Oh ,  Kap-Soo Yoon ,  Jae-Ho Choi ,  Seong-Hun Kim

Inventor： Sung Ryul Kim ,  Yong-Mo Choi ,  Sung-Hoon Yang ,  Hwa-Yeul Oh ,  Kap-Soo Yoon ,  Jae-Ho Choi ,  Seong-Hun Kim

IPC: G02F1/1343 ,  B32B15/04 ,  B32B7/02 ,  H05H1/24 ,  H05K1/09

CPC classification number: G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  Y10T428/24975

Abstract: Provided are a metal line, a method of forming the same, and a display using the same. To increase resistance of a metal line having a multilayered structure of CuO/Cu and prevent blister formation, a plasma treatment is performed using a nitrogen-containing gas and a silicon-containing gas or using a hydrogen or argon as and the silicon-containing gas. Accordingly, a plasma treatment layer such as a SiNx or Si layer is thinly formed on the copper layer, thereby preventing an increase in resistance of the copper layer and also preventing blister formation caused by the damage of a copper oxide layer. Consequently, it is possible to improve the reliability of a copper line and thus enhance the reliability of a device.

Abstract translation: 提供一种金属线，其形成方法和使用该线的显示器。 为了增加具有CuO / Cu多层结构的金属线的电阻并防止起泡形成，使用含氮气体和含硅气体或使用氢或氩作为含硅气体进行等离子体处理 。 因此，在铜层上薄膜地形成诸如SiN x或Si层的等离子体处理层，从而防止铜层的电阻增加，并且还防止由氧化铜层损坏引起的起泡形成。 因此，可以提高铜线的可靠性，从而提高装置的可靠性。

公开(公告)号：US20090180045A1

公开(公告)日：2009-07-16

申请号：US12353152

申请日：2009-01-13

Applicant: Kap-Soo Yoon ,  Sung-Hoon Yang ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

Inventor： Kap-Soo Yoon ,  Sung-Hoon Yang ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

IPC: G02F1/1368 ,  H01L27/08 ,  H01L29/02

CPC classification number: G02F1/1368 ,  G02F2202/108 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869

Abstract: Provided are a display substrate and a display device including the same. The display substrate includes: gate wiring; a first semiconductor pattern formed on the gate wiring and having a first energy bandgap; a second semiconductor pattern formed on the first semiconductor pattern and having a second energy bandgap which is greater than the first energy bandgap; data wiring formed on the first semiconductor pattern; and a pixel electrode electrically connected to the data wiring. Because the second energy bandgap is larger than the first energy bandgap, a quantum well is formed in the first semiconductor pattern, enhancing electron mobility therein.

Abstract translation: 提供了一种显示基板和包括该基板的显示装置。 显示基板包括：栅极布线; 形成在所述栅极布线上并具有第一能量带隙的第一半导体图案; 形成在所述第一半导体图案上并具有大于所述第一能带隙的第二能带隙的第二半导体图案; 形成在第一半导体图案上的数据布线; 以及与数据配线电连接的像素电极。 由于第二能量带隙大于第一能带隙，所以在第一半导体图案中形成量子阱，增强其中的电子迁移率。

公开(公告)号：US20090167974A1

公开(公告)日：2009-07-02

申请号：US12261470

申请日：2008-10-30

Applicant: Jae-ho CHOI ,  Sung-hoon YANG ,  Kap-soo YOON ,  Sung-ryul KIM ,  Hwa-yeul OH ,  Yong-mo CHOI

Inventor： Jae-ho CHOI ,  Sung-hoon YANG ,  Kap-soo YOON ,  Sung-ryul KIM ,  Hwa-yeul OH ,  Yong-mo CHOI

IPC: G02F1/136 ,  H01L29/22 ,  H01L21/34

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L27/1225

Abstract: A display substrate, a display device including the display substrate, and a method of fabricating the display substrate are provided. The display substrate includes a gate electrode; a gate-insulating layer disposed on the gate electrode; an oxide semiconductor pattern disposed on the gate-insulating layer; a source electrode disposed on the oxide semiconductor pattern; and a drain electrode disposed on the oxide semiconductor pattern and separated from the source electrode, wherein at least one portion of at least one of the gate-insulating layer or the oxide semiconductor pattern is plasma-processed.

Abstract translation: 提供了显示基板，包括显示基板的显示装置和制造显示基板的方法。 显示基板包括栅电极; 设置在所述栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的氧化物半导体图案; 设置在所述氧化物半导体图案上的源电极; 以及设置在所述氧化物半导体图案上并与所述源电极分离的漏电极，其中所述栅极绝缘层或所述氧化物半导体图案中的至少一个的至少一部分被等离子体处理。

公开(公告)号：US20080258143A1

公开(公告)日：2008-10-23

申请号：US12100436

申请日：2008-04-10

Applicant: Sung-Ryul KIM ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Jae-Ho CHOI ,  Hwa-Yeul OH ,  Yong-Mo CHOI

Inventor： Sung-Ryul KIM ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Jae-Ho CHOI ,  Hwa-Yeul OH ,  Yong-Mo CHOI

IPC: H01L29/786 ,  H01L21/36

CPC classification number: H01L29/78618 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/7869

Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.

Abstract translation: 制造薄膜晶体管（“TFT”）基板的方法包括在基板上形成包括栅电极的第一导电图案组，在第一导电图案组上形成栅极绝缘层，形成半导体层和欧姆接触层 通过图案化非晶硅层和氧化物半导体层，在栅极绝缘层上，通过图案化数据金属层，在欧姆接触层上形成包括源电极和漏电极的第二导电图案组，形成包括接触的保护层 并且在保护层的接触孔上形成像素电极。 还提供了包括由氧化物半导体形成的欧姆接触层的TFT基板。

公开(公告)号：US20080078992A1

公开(公告)日：2008-04-03

申请号：US11859203

申请日：2007-09-21

Applicant: Sung-hoon YANG ,  So-woon KIM ,  Tae-hyung Hwang ,  Yeon-joo Kim ,  Soo-wan Yoon ,  Chong-chul Chai

Inventor： Sung-hoon YANG ,  So-woon KIM ,  Tae-hyung Hwang ,  Yeon-joo Kim ,  Soo-wan Yoon ,  Chong-chul Chai

IPC: H01L51/10

CPC classification number: H01L27/283 ,  H01L27/285 ,  H01L27/3262

Abstract: A thin film transistors (TFTs) substrate is structured to maintain as constant across the area of the substrate a kickback voltage due to Miller capacitance between the drain and gate of each TFT even in the presence of manufacturing induced misalignments between the drain electrodes and corresponding gate lines. Each thin film transistor includes a gate electrode, an active layer formed on the gate electrode so as to overlap the gate electrode, first and second source electrodes respectively connected to first and second data lines each of which crosses the gate line while being insulated from the gate line, and an elongated drain electrode located between the first and second source electrodes and disposed over the gate electrode so as to a crossing length of the drain electrode is larger than an underlying width of the gate electrode such that misalignment induced shifts of the position of the gate electrode relative to the drain electrode does not substantially change overlap area between the two.

Abstract translation: 薄膜晶体管（TFT）衬底被构造成即使在漏电极和对应的栅极之间的制造引起的不对准的情况下，由于每个TFT的漏极和栅极之间的米勒电容也会在衬底的面积上保持一定的反冲电压 线条。 每个薄膜晶体管包括栅电极，形成在栅电极上以与栅电极重叠的有源层，分别连接到第一和第二数据线的第一和第二源电极，每个第一和第二数据线与栅极线交叉，同时与 栅极线和位于第一和第二源电极之间并设置在栅电极之上的细长漏极，以使漏电极的交叉长度大于栅电极的下伏宽度，使得未对准引起位置移动 相对于漏电极的栅极电极基本上不改变两者之间的重叠面积。