公开(公告)号：US5846863A

公开(公告)日：1998-12-08

申请号：US779469

申请日：1997-01-08

Applicant: Woon-kyung Lee ,  Sung-bu Jun

Inventor： Woon-kyung Lee ,  Sung-bu Jun

IPC: G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  H01L21/8234

CPC classification number: H01L27/1126 ,  G11C17/123 ,  G11C17/126 ,  H01L27/112

Abstract: A semiconductor memory device and a method for manufacturing the same are disclosed. The device includes a plurality of active regions repeatedly formed extending in parallel to each other, a device isolation region, a plurality of first gate electrodes repeatedly arranged being perpendicular to the active region and device isolation region, a source/drain region formed by being self-aligned ion-implanted into the first gate electrode, active region, and device isolation region, and a second gate electrode located between the first gate electrodes, extending in parallel to the first gate electrode, sharing the source/drain with the first gate electrode, and using the device isolation region as a channel. Thus, cell integration can be enhanced, and high speed operation and excellent yields can be easily ensured.

Abstract translation: 公开了一种半导体存储器件及其制造方法。 该器件包括重复形成的彼此平行延伸的多个有源区，器件隔离区，与有源区和器件隔离区垂直的反复排列的多个第一栅极，由自身形成的源极/漏极区 位于第一栅电极，有源区和器件隔离区中的对准离子注入，以及位于第一栅电极之间的平行于第一栅电极延伸的第二栅极，与第一栅电极共用源极/漏极 ，并使用设备隔离区域作为通道。 因此，能够提高电池积分，能够容易地确保高速运转和良好的收率。

公开(公告)号：US5721698A

公开(公告)日：1998-02-24

申请号：US604785

申请日：1996-02-23

Applicant: Woon-kyung Lee ,  Sung-bu Jun

Inventor： Woon-kyung Lee ,  Sung-bu Jun

IPC: G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  G11C17/00 ,  H01L29/68

CPC classification number: H01L27/1126 ,  G11C17/123 ,  G11C17/126 ,  H01L27/112

Abstract: A semiconductor memory device and a method for manufacturing the same are disclosed. The device includes a plurality of active regions repeatedly formed extending in parallel to each other, a device isolation region, a plurality of first gate electrodes repeatedly arranged being perpendicular to the active region and device isolation region, a source/drain region formed by being self-aligned ion-implanted into the first gate electrode, active region, and device isolation region, and a second gate electrode located between the first gate electrodes, extending in parallel to the first gate electrode, sharing the source/drain with the first gate electrode, and using the device isolation region as a channel. Thus, cell integration can be enhanced, and high speed operation and excellent yields can be easily ensured.

Abstract translation: 公开了一种半导体存储器件及其制造方法。 该器件包括重复形成的彼此平行延伸的多个有源区，器件隔离区，与有源区和器件隔离区垂直的反复排列的多个第一栅极，由自身形成的源极/漏极区 位于第一栅电极，有源区和器件隔离区中的对准离子注入，以及位于第一栅电极之间的平行于第一栅电极延伸的第二栅极，与第一栅电极共用源极/漏极 ，并使用设备隔离区域作为通道。 因此，能够提高电池积分，能够容易地确保高速运转和良好的收率。

公开(公告)号：US09306041B2

公开(公告)日：2016-04-05

申请号：US14156607

申请日：2014-01-16

Applicant: Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

Inventor： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

Abstract translation: 垂直型半导体器件包括包括第一和第二字线的第一和第二字线结构。 字线围绕多个柱结构，其被提供以将字线连接到相应的字符串选择线。 连接图案将相邻的第一和第二字线的对电连接在同一平面中。 该设备可以是非易失性存储设备或不同类型的设备。

公开(公告)号：US09087861B2

公开(公告)日：2015-07-21

申请号：US14156781

申请日：2014-01-16

Applicant: Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

Inventor： Sung-Min Hwang ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Won-Seok Cho

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

Abstract translation: 制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘 部分堆叠结构以形成初步的阶梯状图案结构。 初步阶形形状图案结构具有阶梯形边缘部分。 形成与基板表面接触的柱结构。 部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。 第二开口部分切割下牺牲层的至少边缘部分。

公开(公告)号：US20140199815A1

公开(公告)日：2014-07-17

申请号：US14156781

申请日：2014-01-16

Applicant: Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

Inventor： Sung-Min HWANG ,  Han-Soo KIM ,  Woon-Kyung LEE ,  Won-Seok CHO

IPC: H01L29/66

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion. A pillar structure making contact with a surface of the substrate is formed. The preliminary stepped shape pattern structure, the lower sacrificial layer, and the first and second lower insulating layers are partially etched to form a first opening portion and a second opening portion to form a stepped shape pattern structure. The second opening portion cuts at least an edge portion of the lower sacrificial layer.

Abstract translation: 制造垂直型存储装置的方法包括在基板上堆叠第一下绝缘层，一层下牺牲层和第二下绝缘层，通过堆叠牺牲层和绝缘层形成堆叠结构，并蚀刻边缘 部分堆叠结构以形成初步阶形状图案结构。 初步阶形形状图案结构具有阶梯形边缘部分。 形成与基板表面接触的柱结构。 部分地蚀刻初步阶形状图案结构，下牺牲层和第一下绝缘层和第二下绝缘层，以形成第一开口部分和第二开口部分，以形成台阶状图形结构。 第二开口部分切割下牺牲层的至少边缘部分。

公开(公告)号：US20130228849A1

公开(公告)日：2013-09-05

申请号：US13775833

申请日：2013-02-25

Applicant: Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

Inventor： Ju-Hyung Kim ,  Chang-Seok Kang ,  Woon-Kyung Lee

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/7926

Abstract: A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.

Abstract translation: 非易失性存储器件包括彼此间隔开并且彼此堆叠的沟道图案，第一层间电介质膜和第二层间电介质膜，布置在第一层间电介质膜和第二层间电介质膜之间的栅极图案，阱 设置在栅极图案和沟道图案之间的层，以及设置在沟道图案和第一层间电介质膜之间以及沟道图案和第二层间电介质膜之间的电荷扩展抑制层。 电荷扩散抑制层可以包括其表面内部或其表面上的电荷。 电荷扩散抑制层包括金属氧化物膜或金属氮化物膜或具有比氧化硅膜更大的介电常数的金属氧氮化物膜中的至少一种。

公开(公告)号：US08456918B2

公开(公告)日：2013-06-04

申请号：US12405826

申请日：2009-03-17

Applicant: Dong-Yean Oh ,  Woon-Kyung Lee ,  Jai Hyuk Song ,  Chang-Sub Lee

Inventor： Dong-Yean Oh ,  Woon-Kyung Lee ,  Jai Hyuk Song ,  Chang-Sub Lee

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL , a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors. The excessive increase of Vch2 is prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.

Abstract translation: 闪速存储器件包括一块NAND单元单元，该块中的每个NAND单元单元包括由多个n个字线控制的n个存储单元晶体管MC，并串联连接在连接到位线的串选择晶体管SST和 接地选择晶体管GST。 当编程电压Vpgm被施加到所选字线WL时，截止电压Vss被施加到靠近接地选择晶体管GST的附近未选字线，以将第一本地信道Ch1与第二本地信道Ch2隔离。 当所选择的字线WL i的位置i增加到接近于SST时，第二通道电位Vch2会过度增加，导致错误。 通过修改施加到串选择线（SSL）和/或位线（BL）的电压或施加到未选择字线（WL ），只有当所选择的字线WL i位置i等于或大于预定（存储的）位置号码x时。 如果实现增量步进脉冲编程（ISPP），只有当ISPP循环计数j等于或大于预定（存储）的关键循环数y时，才施加电压。