公开(公告)号：US07005903B2

公开(公告)日：2006-02-28

申请号：US10726297

申请日：2003-12-02

Applicant: Hong H. Chan ,  Jeffrey E. Smith ,  Yongping Fan ,  Prantik K. Nag

Inventor： Hong H. Chan ,  Jeffrey E. Smith ,  Yongping Fan ,  Prantik K. Nag

IPC: H03K5/12

CPC classification number: H03K19/00384

Abstract: An output buffer generates an output signal having a plurality of low-to-high (LH) and high-to-low (HL) signal transitions, with each of the signal transitions having a clock-to-output delay. A pre-driver having a first and a second stage generates a reshaped waveform to trigger the LH and HL signal transitions of the output signal, with the first stage generating an initial waveform and the second stage modifying the initial waveform to generate the reshaped waveform based at least in part on a feedback reflective of a difference in the clock-to-output delays of the LH and HL signal transitions.

Abstract translation: 输出缓冲器产生具有多个低到高（LH）和高到低（HL）信号转换的输出信号，其中每个信号转换具有时钟到输出延迟。 具有第一和第二阶段的预驱动器产生重构波形以触发输出信号的LH和HL信号转换，其中第一级产生初始波形，第二级修改初始波形以产生基于重新形成的波形 至少部分地基于反映LH和HL信号转换的时钟到输出延迟的差异的反馈。

公开(公告)号：US20050116752A1

公开(公告)日：2005-06-02

申请号：US10726297

申请日：2003-12-02

Applicant: Hong Chan ,  Jeffrey Smith ,  Yongping Fan ,  Prantik Nag

Inventor： Hong Chan ,  Jeffrey Smith ,  Yongping Fan ,  Prantik Nag

IPC: H03K5/12 ,  H03K19/003

CPC classification number: H03K19/00384

Abstract: An output buffer generates an output signal having a plurality of low-to-high (LH) and high-to-low (HL) signal transitions, with each of the signal transitions having a clock-to-output delay. A pre-driver having a first and a second stage generates a reshaped waveform to trigger the LH and HL signal transitions of the output signal, with the first stage generating an initial waveform and the second stage modifying the initial waveform to generate the reshaped waveform based at least in part on a feedback reflective of a difference in the clock-to-output delays of the LH and HL signal transitions.

Abstract translation: 输出缓冲器产生具有多个低到高（LH）和高到低（HL）信号转换的输出信号，其中每个信号转换具有时钟到输出延迟。 具有第一和第二阶段的预驱动器产生重构波形以触发输出信号的LH和HL信号转换，其中第一级产生初始波形，第二级修改初始波形以产生基于重新形成的波形 至少部分地基于反映LH和HL信号转换的时钟到输出延迟的差异的反馈。

公开(公告)号：US08901994B2

公开(公告)日：2014-12-02

申请号：US13997645

申请日：2011-12-30

Applicant: Yongping Fan

Inventor： Yongping Fan

IPC: H03K5/00 ,  H03L7/093

CPC classification number: H03L7/093 ,  H03H19/004 ,  H03L7/0893

Abstract: A loop filter is described. The loop filter has first and second inputs and an output. A loop filter capacitor is coupled to the loop filter output. Sample switches are coupled to the second loop filter input. A voltage divider is coupled to reset switches. Switched capacitors are coupled to sample switches, the reset switches, the loop filter capacitor, and the loop filter output.

Abstract translation: 描述环路滤波器。 环路滤波器具有第一和第二输入和输出。 环路滤波电容器耦合到环路滤波器输出。 采样开关耦合到第二环路滤波器输入。 分压器耦合到复位开关。 开关电容器耦合到采样开关，复位开关，环路滤波电容器和环路滤波器输出。

公开(公告)号：US20140266308A1

公开(公告)日：2014-09-18

申请号：US13836951

申请日：2013-03-15

Applicant: Gennady Goltman ,  Yongping Fan

Inventor： Gennady Goltman ,  Yongping Fan

IPC: H03L7/085 ,  G01R23/02

CPC classification number: H03L5/00 ,  G01R19/04 ,  G01R19/16576 ,  H03L7/099

Abstract: In some embodiments, disclosed is an AC amplitude detector to compare the magnitude of an AC signal against a detector threshold level and to provide an indication as to whether the AC magnitude is larger or smaller than the detector threshold level.

Abstract translation: 在一些实施例中，公开了一种AC振幅检测器，用于将AC信号的幅度与检测器阈值电平进行比较，并提供关于AC幅度是大于还是小于检测器阈值电平的指示。

公开(公告)号：US20110267150A1

公开(公告)日：2011-11-03

申请号：US12770230

申请日：2010-04-29

Applicant: Yongping Fan ,  Jing Li ,  Ian A. Young

Inventor： Yongping Fan ,  Jing Li ,  Ian A. Young

IPC: H03J7/04

CPC classification number: H03L1/02 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1234 ,  H03B5/124 ,  H03B5/1265 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/103 ,  H03L7/18

Abstract: A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.

Abstract translation: 公开了用于LC-PLL系统中的自动频率控制和数字温度补偿的混合信号电路架构。 一些实施例允许诸如微处理器和芯片组的产品的大量制造以及采用LC-PLL技术的其它电路。 在一些实施例中，可以选择各种电容器负载以补偿与过程，电压，温度和参考频率相关联的变化。 此外，根据一些实施例，可以选择性地使用多支脚电容器组来进一步补偿温度变化后锁定。 在一些实施例中可以使用可编程定时器，以便在评估感兴趣的参数之前允许循环结算。

公开(公告)号：US07583151B2

公开(公告)日：2009-09-01

申请号：US11701303

申请日：2007-01-31

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L5/00 ,  H03B5/08

CPC classification number: H03L5/00 ,  H03L7/099 ,  H03L2207/06

Abstract: Disclosed are circuits and methods to control the amplitude of a signal generated by a VCO.

Abstract translation: 公开了用于控制由VCO产生的信号的幅度的电路和方法。

公开(公告)号：US20080122545A1

公开(公告)日：2008-05-29

申请号：US11592591

申请日：2006-11-03

Applicant: Yongping Fan ,  Ian Young

Inventor： Yongping Fan ,  Ian Young

IPC: H03L7/099 ,  H03L7/085 ,  H03K3/353 ,  H03L7/089

CPC classification number: H03L7/0995 ,  H03K5/133 ,  H03K2005/00039 ,  H03K2005/00136 ,  H03L7/0891 ,  H03L7/18

Abstract: A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down current. For each delay cell, the gate of the biased nMOSFET is biased by the control voltage provided by the phase locked loop, and the gate of the biased pMOSFET is biased at a bias voltage provided by the feedback loop. The biasing of the pMOSFETs is adjusted so that the pull-up and pull-down currents for each delay cell are matched, thereby providing a 50% duty cycle and good jitter performance over process, supply voltage variations, and temperature variations. Because only the feedback loop has non-zero static current, low power is expected. Other embodiments are described and claimed.

Abstract translation: 具有压控振荡器的锁相环，其中压控振荡器包括反馈回路和以环形连接的延迟单元。 每个延迟单元具有偏置的pMOSFET以提供上拉电流和偏置的nMOSFET以提供下拉电流。 对于每个延迟单元，偏置的nMOSFET的栅极被由锁相环提供的控制电压偏置，并且偏置的pMOSFET的栅极被偏置在由反馈环路提供的偏置电压。 调整pMOSFET的偏置，使得每个延迟单元的上拉和下拉电流匹配，从而提供50％的占空比以及在处理，电源电压变化和温度变化方面的良好的抖动性能。 因为只有反馈回路具有非零静态电流，所以预期功耗低。 描述和要求保护其他实施例。

公开(公告)号：US07202715B1

公开(公告)日：2007-04-10

申请号：US11232840

申请日：2005-09-21

Applicant: Yongping Fan

Inventor： Yongping Fan

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03K5/133 ,  H03K2005/00039

Abstract: Matched current delay cells and a delay locked loop based on such cells that may be used for timing data interfaces between semiconductor devices is described. In one embodiment, the delay cell includes a delay cell having a PMOS portion and a NMOS portion, gates of the PMOS portion being coupled to a vp-bias and gates of the NMOS portion being coupled to a vn-bias, the delay cell further being coupled to a reference clock to drive a pulse output of the delay cell, a first bias generation circuit to generate the vn-bias based on a phase comparison of the pulse output to the reference clock, and a second bias generation circuit to generate the vp-bias based on a reference voltage and the vn-bias.

Abstract translation: 描述了基于可用于半导体器件之间的定时数据接口的这样的单元的匹配的当前延迟单元和延迟锁定环。 在一个实施例中，延迟单元包括具有PMOS部分和NMOS部分的延迟单元，PMOS部分的栅极耦合到vp偏置，并且NMOS部分的栅极耦合到vn偏置，延迟单元进一步 耦合到参考时钟以驱动所述延迟单元的脉冲输出;第一偏置产生电路，用于基于所述脉冲输出与所述参考时钟的相位比较产生所述vn偏置;以及第二偏置产生电路， 基于参考电压和vn偏置的vp偏置。

公开(公告)号：US5610413A

公开(公告)日：1997-03-11

申请号：US484088

申请日：1995-06-07

Applicant: Yongping Fan ,  Jung Han ,  Arto V. Nurmikko ,  Robert L. Gunshor ,  Li He

Inventor： Yongping Fan ,  Jung Han ,  Arto V. Nurmikko ,  Robert L. Gunshor ,  Li He

IPC: H01L21/36 ,  H01L21/44 ,  H01L27/15 ,  H01L33/06 ,  H01L33/08 ,  H01L33/14 ,  H01L33/26 ,  H01L33/28 ,  H01L33/40 ,  H01S5/042 ,  H01S5/223 ,  H01S5/347 ,  H01L33/00

CPC classification number: H01S5/347 ,  B82Y20/00 ,  H01L21/02395 ,  H01L21/024 ,  H01L21/02417 ,  H01L21/02469 ,  H01L21/02485 ,  H01L21/0251 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/02568 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/44 ,  H01L33/06 ,  H01L33/08 ,  H01L33/14 ,  H01S5/0421 ,  H01L27/156 ,  H01L33/26 ,  H01L33/28 ,  H01L33/40 ,  H01S5/2231

Abstract: Group II-VI compound semiconductor light emitting devices which include at least one II-VI quantum well region of a well layer disposed between first and second barrier layers is disclosed. The quantum well region is sandwiched between first and second cladding layers of a II-VI semiconductor material. The first cladding layer is formed on and lattice matched to the first barrier layer and to a substrate of a III-V compound semiconductor material. The second cladding layer is lattice matched to the second barrier layer. The quantum well layer comprises a II-VI compound semiconductor material having the formula A.sub.x B.sub.(1-x) C wherein A and B are two different elements from Group II and C is at least one element from Group VI. When the second cladding layer has a p-type conductivity, a graded bandgap ohmic contact according to the present invention can be utilized. The graded bandgap contact can be a single continuously graded II-VI p-type region or a plurality of cells with each of the cells having first and second thin layers of first and second p-type II-VI semiconductor materials respectively. Another embodiment of the present invention discloses a monolithic multicolor light emitting element capable of emitting four colors and a method for fabricating same. The monolithic multicolor element includes four II-VI semiconductor light emitting devices formed on a single III-V substrate.

Abstract translation: 公开了包括设置在第一和第二阻挡层之间的阱层的至少一个II-VI量子阱区的II-VI族化合物半导体发光器件。 量子阱区夹在II-VI半导体材料的第一和第二覆层之间。 第一包层与第一阻挡层和III-V族化合物半导体材料的衬底形成并晶格匹配。 第二包层与第二阻挡层晶格匹配。 量子阱层包括具有式AxB（1-x）C的II-VI化合物半导体材料，其中A和B是来自组II的两个不同元素，C是来自第VI族的至少一种元素。 当第二包覆层具有p型导电性时，可以使用根据本发明的渐变带隙欧姆接触。 分级带隙接触可以是单个连续分级的II-VI p型区域或多个单元，其中每个单元分别具有第一和第二p型II-VI半导体材料的第一和第二薄层。 本发明的另一实施例公开了能够发射四种颜色的单片多色发光元件及其制造方法。 单片多色元件包括形成在单个III-V衬底上的四个II-VI半导体发光器件。