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公开(公告)号：US09367474B2
公开(公告)日：2016-06-14
申请号：US13915911
申请日：2013-06-12
Applicant: Apple Inc.
Inventor： Shailendra S. Desai , Gurjeet S. Saund , Deniz Balkan , James Wang
IPC: G06F12/0893 , G06F12/08 , G06F12/12
CPC classification number: G06F12/0893 , G06F12/0802 , G06F12/0888 , G06F12/12 , Y02D10/13
Abstract: Systems and methods for translating cache hints between different protocols within a SoC. A requesting agent within the SoC generates a first cache hint for a transaction, and the first cache hint is compliant with a first protocol. The first cache hint can be set to a reserved encoding value as defined by the first protocol. Prior to the transaction being sent to the memory subsystem, the first cache hint is translated into a second cache hint. The memory subsystem recognizes cache hints which are compliant with a second protocol, and the second cache hint is compliant with the second protocol.
Abstract translation: 用于翻译SoC中不同协议之间的缓存提示的系统和方法。 SoC中的请求代理生成用于事务的第一高速缓存提示，并且第一高速缓存提示符合第一协议。 第一个缓存提示可以设置为第一个协议定义的保留编码值。 在将事务发送到存储器子系统之前，第一高速缓存提示被转换成第二高速缓存提示。 存储器子系统识别符合第二协议的高速缓存提示，并且第二高速缓存提示符合第二协议。
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公开(公告)号：US09317102B2
公开(公告)日：2016-04-19
申请号：US13733775
申请日：2013-01-03
Applicant: Apple Inc.
Inventor： Muditha Kanchana , Gurjeet S. Saund , Harshavardhan Kaushikkar , Erik P. Machnicki , Seye Ewedemi
CPC classification number: G06F1/3275 , G06F1/3225 , G11C5/144 , Y02D10/14
Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.
Abstract translation: 公开了关于降低集成电路中的功耗的技术。 在一个实施例中，一种装置包括具有一组标签结构的缓存和电源管理单元。 功率管理单元被配置为响应于被断电的高速缓存而将重复的一组标签结构断电。 在一个实施例中，高速缓存被配置为向电力管理单元提供高速缓存是否包括有效数据的指示。 在这样的实施例中，功率管理单元被配置为响应于缓存指示高速缓存不包括有效数据的高速缓存来关闭高速缓存。 在一些实施例中，重复的标签结构集合位于被配置为保持高速缓存和存储器之间的一致性的相干点内。
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公开(公告)号：US09201791B2
公开(公告)日：2015-12-01
申请号：US13736245
申请日：2013-01-08
Applicant: Apple Inc.
Inventor： Gurjeet S. Saund , Harshavardhan Kaushikkar
CPC classification number: G06F12/0815 , G06F9/46 , G06F9/466 , G06F12/0811 , G06F13/18
Abstract: Systems and methods for maintaining an order of transactions in the coherence point. The coherence point stores attributes associated with received transactions in an input request queue (IRQ). When a new transaction is received with a device ordered attribute, the IRQ is searched for other entries with the same flow ID as the new transaction. If one or more matches are found, the new transaction entry points to the entry for the most recently received transaction with the same flow ID. The new transaction is prevented from exiting the coherence point until the transaction it points to has been sent to its destination.
Abstract translation: 在一致性点保持交易顺序的系统和方法。 相干点存储与输入请求队列（IRQ）中的接收事务相关联的属性。 当接收到具有设备排序属性的新事务时，IRQ将搜索与新事务具有相同流ID的其他条目。 如果找到一个或多个匹配，则新的事务条目指向具有相同流ID的最近收到的事务的条目。 新交易被阻止退出连贯点，直到其指向的交易已发送到其目的地。
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公开(公告)号：US09170768B2
公开(公告)日：2015-10-27
申请号：US13726437
申请日：2012-12-24
Applicant: Apple Inc.
Inventor： Jason M. Kassoff , Kevin C. Wong , Brian P. Lilly , Gurjeet S. Saund
CPC classification number: G06F5/06 , G06F13/38 , G06F13/382
Abstract: Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.
Abstract translation: 用于管理总线结构中快速到慢速链接的系统和方法。 一对链路接口单元连接具有时钟不匹配的代理。 每个链路接口单元包括用于存储通过时钟域穿越发送的事务的异步FIFO。 当新事务的命令准备好发送，而前一个事务的数据仍然被发送时，链接接口单元阻止发送先前事务的最后数据节拍。 相反，在一个或多个时钟周期的延迟之后，最后的数据跳转与新事务的命令重叠。
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公开(公告)号：US12086919B2
公开(公告)日：2024-09-10
申请号：US18344294
申请日：2023-06-29
Applicant: Apple Inc.
Inventor： Arthur Y Zhang , Ray L. Chang , Timothy R. Oriol , Ling Su , Gurjeet S. Saund , Guy Cote , Jim C. Chou , Hao Pan , Tobias Eble , Avi Bar-Zeev , Sheng Zhang , Justin A. Hensley , Geoffrey Stahl
Abstract: A mixed reality system that includes a device and a base station that communicate via a wireless connection The device may include sensors that collect information about the user's environment and about the user. The information collected by the sensors may be transmitted to the base station via the wireless connection. The base station renders frames or slices based at least in part on the sensor information received from the device, encodes the frames or slices, and transmits the compressed frames or slices to the device for decoding and display. The base station may provide more computing power than conventional stand-alone systems, and the wireless connection does not tether the device to the base station as in conventional tethered systems. The system may implement methods and apparatus to maintain a target frame rate through the wireless link and to minimize latency in frame rendering, transmittal, and display.
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Patent Agency Ranking
公开(公告)号：US11804019B2
公开(公告)日：2023-10-31
申请号：US17693881
申请日：2022-03-14
Applicant: Apple Inc.
Inventor： Ranjit Desai , Venu M. Duggineni , Perry A. Caro , Alexsandr M. Movshovich , Gurjeet S. Saund
CPC classification number: G06T19/006 , G06F3/011 , G06T3/00 , G06T9/00 , G10L25/51 , H04L65/61 , H04L65/70
Abstract: One implementation forms a composited stream of computer-generated reality (CGR) content using multiple data streams related to a CGR experience to facilitate recording or streaming. A media compositor obtains a first data stream of rendered frames and a second data stream of additional data. The rendered frame content (e.g., 3D models) represents real and virtual content rendered during a CGR experience at a plurality of instants in time. The additional data of the second data stream relates to the CGR experience, for example, relating to audio, audio sources, metadata identifying detected attributes of the CGR experience, image data, data from other devices involved in the CGR experience, etc. The media compositor forms a composited stream that aligns the rendered frame content with the additional data for the plurality of instants in time, for example, by forming time-stamped, n-dimensional datasets (e.g., images) corresponding to individual instants in time.
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公开(公告)号：US11308696B2
公开(公告)日：2022-04-19
申请号：US16533053
申请日：2019-08-06
Applicant: Apple Inc.
Inventor： Ranjit Desai , Venu M. Duggineni , Perry A. Caro , Aleksandr M. Movshovich , Gurjeet S. Saund
Abstract: One implementation forms a composited stream of computer-generated reality (CGR) content using multiple data streams related to a CGR experience to facilitate recording or streaming. A media compositor obtains a first data stream of rendered frames and a second data stream of additional data. The rendered frame content (e.g., 3D models) represents real and virtual content rendered during a CGR experience at a plurality of instants in time. The additional data of the second data stream relates to the CGR experience, for example, relating to audio, audio sources, metadata identifying detected attributes of the CGR experience, image data, data from other devices involved in the CGR experience, etc. The media compositor forms a composited stream that aligns the rendered frame content with the additional data for the plurality of instants in time, for example, by forming time-stamped, n-dimensional datasets (e.g., images) corresponding to individual instants in time.
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公开(公告)号：US09495318B2
公开(公告)日：2016-11-15
申请号：US14089237
申请日：2013-11-25
Applicant: Apple Inc.
Inventor： Deniz Balkan , Gurjeet S. Saund , Jim J. Lin , Timothy R. Paaske , Ben D. Jarrett
IPC: G06F13/00 , G06F13/40 , G06F13/362 , G06F13/364
CPC classification number: G06F13/405 , G06F13/362 , G06F13/364 , G06F13/4027
Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.
Abstract translation: 公开了桥单元和系统的实施例，其可以允许处理围栏命令发送到多个桥单元。 每个桥单元可以处理由主单元生成的多个交易的相应部分。 主单元可以被配置为向每个桥单元发送fence命令，这可能阻止命令的处理。 每个桥单元可以被配置为确定包括在其多个事务的相应部分中的所有事务是否已经完成。 一旦每个桥接单元已经确定所有其他桥接单元已经接收到围栏命令，并且所有其他桥接单元已经完成了在接收到围栏命令之前接收到的多个事务的各自部分，则所有桥单元可以执行fence命令 。
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公开(公告)号：US09280471B2
公开(公告)日：2016-03-08
申请号：US14081549
申请日：2013-11-15
Applicant: Apple Inc.
Inventor： Manu Gulati , Harshavardhan Kaushikkar , Gurjeet S. Saund , Wei-Han Lien , Gerard R. Williams, III , Sukalpa Biswas , Brian P. Lilly , Shinye Shiu
CPC classification number: G06F12/084 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0822 , G06F2212/1028 , Y02D10/13
Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.
Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。
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30.发明申请Interfacing Dynamic Hardware Power Managed Blocks and Software Power Managed Blocks 审中-公开动态硬件电源管理块和软件电源管理块的接口公开(公告)号：US20160026234A1
公开(公告)日：2016-01-28
申请号：US14876922
申请日：2015-10-07
Applicant: Apple Inc.
Inventor： Erik P. Machnicki , Gurjeet S. Saund , Munetoshi Fukami , Shane J. Keil , Chaitanya Kosaraju , Erdem Guleyupoglu , Jason M. Kassoff , Kevin C. Wong
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3206 , G06F1/3246 , G06F1/329 , G06F1/3293 , Y02D10/24 , Y02D50/20
Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.
Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。
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