公开(公告)号：US11895816B2

公开(公告)日：2024-02-06

申请号：US17112479

申请日：2020-12-04

Applicant: Arm Limited

Inventor： Amit Chhabra ,  Brian Tracy Cline

IPC: H01L21/8238 ,  H10B10/00 ,  H01L23/528 ,  H01L27/06 ,  H01L27/092 ,  H01L27/02

CPC classification number: H10B10/12 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0922

Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.

公开(公告)号：US11625522B2

公开(公告)日：2023-04-11

申请号：US16861286

申请日：2020-04-29

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Kyungwook Chang ,  Brian Tracy Cline ,  Ebbin Raney Southerland, Jr.

IPC: G06F30/34 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312

Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

公开(公告)号：US20220181331A1

公开(公告)日：2022-06-09

申请号：US17112479

申请日：2020-12-04

Applicant: Arm Limited

Inventor： Amit Chhabra ,  Brian Tracy Cline

IPC: H01L27/11 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8238

Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.

公开(公告)号：US10599806B2

公开(公告)日：2020-03-24

申请号：US15939047

申请日：2018-03-28

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/522

Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without the inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without the inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without the inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized or legal locations.

公开(公告)号：US20180225402A9

公开(公告)日：2018-08-09

申请号：US14528314

申请日：2014-10-30

Applicant: ARM Limited

Inventor： Paul DE DOOD ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Douglas Ngai Lee ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Yanbin Jiang ,  Emmanuel Jean Marie Olivier Pacaud ,  Matthieu Domonique Henri Pauly ,  Sylvia Xiuhui Li ,  Thanusree Achuthan ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US20180018420A1

公开(公告)日：2018-01-18

申请号：US15210109

申请日：2016-07-14

Applicant: ARM Limited

Inventor： Brian Tracy Cline ,  Gregory Munson Yeric

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/528

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G03F7/2022 ,  G06F17/5045 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00 ,  H01L21/76892 ,  H01L23/528

Abstract: A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout data file to further include mask information having at least a first set of trim features associated with one or more redundant metal portions and one or more active metal portions of the layout data file. The method also comprises determining the one or more redundant metal portions to be perforated. The method further comprises modifying the mask information to further include a second set of trim features for perforating the one or more redundant metal portions. The first set of trim features and the second set of trim features are associated with a trim mask of the SAMP process.

公开(公告)号：US20240081038A1

公开(公告)日：2024-03-07

申请号：US17902798

申请日：2022-09-02

Applicant: Arm Limited

Inventor： Divya Madapusi Srinivas Prasad ,  David Victor Pietromonaco ,  Brian Tracy Cline ,  Mudit Bhargave

IPC: H01L27/108

CPC classification number: H01L27/108

Abstract: According to one implementation of the present disclosure, a circuit structure is configured to store charge in a charge-based storage element, where the charge-based storage element is disposed at least partially in a shallow-trench-isolation (STI) region of the circuit. According to one implementation of the present disclosure, a method includes: providing a circuit structure disposed on a substrate and a shallow-trench-isolation (STI) region of a circuit; forming an opening of the substrate and the STI region by removing a portion of the substrate and STI region; placing a first liner material in the opening and on remaining portions of the substrate and the STI region; and depositing a first metal layer in the opening on the first liner material.

公开(公告)号：US11569219B2

公开(公告)日：2023-01-31

申请号：US17077532

申请日：2020-10-22

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

IPC: H01L27/02 ,  G06F30/31 ,  H01L21/768 ,  H01L23/535 ,  H01L25/065 ,  H01L25/00

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

公开(公告)号：US11004479B2

公开(公告)日：2021-05-11

申请号：US16833154

申请日：2020-03-27

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Shidhartha Das ,  George McNeil Lattimore ,  Brian Tracy Cline

IPC: G11C5/06 ,  G11C14/00 ,  G11C8/10 ,  G11C13/00

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

公开(公告)号：US20210081508A1

公开(公告)日：2021-03-18

申请号：US16569482

申请日：2019-09-12

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Stephen Lewis Moore ,  Mudit Bhargava

IPC: G06F17/50

Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.