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    Method for adaptive performance optimization of the soc
    22.
    发明授权
    Method for adaptive performance optimization of the soc 有权
    方法适应性能优化的社会

    公开(公告)号：US09261949B2

    公开(公告)日：2016-02-16

    申请号：US13889840

    申请日：2013-05-08

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander J. Branover ,  Ashish Jain ,  Ann M. Ling ,  Maurice B. Steinman

    IPC: G06F1/32 ,  G06F1/20

    CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

    Abstract: An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components.

    Abstract translation: 公开了用于动态调整处理节点和其他组件（诸如外围接口）的组件的功率限制的装置和方法。 该设备包括多个处理节点和其他组件，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置对于至少一个处理节点的第一频率限制。 对于没有可靠的功耗报告或成本或省电原因的组件，初始功率限制设置在保护带功率限制以下。 处理节点的节流量用于调整处理节点和这些组件的功率限制。

    DYNAMIC POWER ALLOCATION BASED ON PHY POWER ESTIMATION
    23.
    发明申请
    DYNAMIC POWER ALLOCATION BASED ON PHY POWER ESTIMATION 有权
    基于物理功率估计的动态功率分配

    公开(公告)号：US20150277521A1

    公开(公告)日：2015-10-01

    申请号：US14225244

    申请日：2014-03-25

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Ashish Jain ,  Alexander J. Branover ,  Guhan Krishnan

    IPC: G06F1/26

    CPC classification number: G06F1/3225 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

    Abstract: A system has a plurality of electronic components including a memory, a PHY coupled to the memory, and one or more other electronic components. Power consumed by the PHY is estimated during operation of the system. Estimating the power consumed by the PHY includes modeling the power consumed by the PHY as a linear function with respect to memory bandwidth. Available power for the PHY is determined based at least in part on the estimated power consumed by the PHY. At least a portion of the available power for the PHY is allocated to at least one of the one or more other components.

    Abstract translation: 系统具有包括存储器，耦合到存储器的PHY和一个或多个其它电子部件的多个电子部件。 在系统运行期间估计PHY消耗的功率。 估计PHY消耗的功率包括将PHY消耗的功率建模为相对于存储器带宽的线性函数。 至少部分地基于PHY消耗的估计功率来确定PHY的可用功率。 用于PHY的可用功率的至少一部分被分配给一个或多个其它组件中的至少一个。

    ESTIMATING LEAKAGE CURRENTS BASED ON RATES OF TEMPERATURE OVERAGES OR POWER OVERAGES
    24.
    发明申请
    ESTIMATING LEAKAGE CURRENTS BASED ON RATES OF TEMPERATURE OVERAGES OR POWER OVERAGES 审中-公开
    基于温度范围或功率的估算漏电流

    公开(公告)号：US20150073611A1

    公开(公告)日：2015-03-12

    申请号：US14021279

    申请日：2013-09-09

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Alexander J. Branover

    IPC: G05B13/02 ,  G01R31/02

    CPC classification number: G01R31/025 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

    Abstract: An operating point of one or more components in a processing device may be set using a leakage current estimated based on at least one of a rate of temperature overages or a rate of power overages. In some embodiments, a power management controller may be used to set an operating point of one or more components in the processing device based on at least one of a rate of temperature overages or a rate of power overages for the component(s).

    Abstract translation: 处理装置中的一个或多个部件的操作点可以使用基于温度超标率或功率超载率中的至少一个估计的泄漏电流来设置。 在一些实施例中，功率管理控制器可以用于基于温度过高的速率或组件的功率过载速率中的至少一个来设置处理设备中的一个或多个组件的工作点。

    Frequency/state based power management thresholds
    25.
    发明授权
    Frequency/state based power management thresholds 有权

    公开(公告)号：US12164353B2

    公开(公告)日：2024-12-10

    申请号：US17936740

    申请日：2022-09-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Shang Yang

    IPC: G06F1/3206

    Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.

    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI
    26.
    发明公开
    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI 审中-公开

    公开(公告)号：US20240334340A1

    公开(公告)日：2024-10-03

    申请号：US18128805

    申请日：2023-03-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Paul Blinzer ,  Chirag Nitinkumar Dhruv ,  Ranjeet Kumar ,  Gia Tung Phan ,  Ashish Jain

    IPC: H04W52/02

    CPC classification number: H04W52/029 ,  H04W52/0274

    Abstract: An apparatus and method for efficiently performing power management for increasing reliable wireless signal transfer performed by mobile computing devices. In various implementations, a computing system includes a network interface and multiple components for processing tasks. The network interface sends, to at least a given component of the multiple components, an indication specifying the corresponding operating frequency ranges used by one or more radio modules used for wireless communication with an access point. The given component determines whether an operating clock frequency of the given component overlaps any of the received operating frequency ranges and associated harmonic frequencies. If so, then the given component changes the operating clock frequency to a frequency that does not overlap any of the received operating frequency ranges and associated harmonic frequencies.

    LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT
    27.
    发明公开
    LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20240319781A1

    公开(公告)日：2024-09-26

    申请号：US18189993

    申请日：2023-03-24

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Gia Tung Phan ,  Randall Brown ,  Ashish Jain

    IPC: G06F1/3234 ,  G06F1/3228 ,  G06F1/3287

    CPC classification number: G06F1/3275 ,  G06F1/3228 ,  G06F1/3287

    Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition. The persistent on-chip memory utilizes synchronous random-access memory that receives a standby power supply reference level that continually supplies a voltage magnitude by not being turned off.

    PLATFORM EFFICIENCY TRACKER
    29.
    发明公开
    PLATFORM EFFICIENCY TRACKER 审中-公开

    公开(公告)号：US20240004448A1

    公开(公告)日：2024-01-04

    申请号：US17853759

    申请日：2022-06-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Eric D. Meyer ,  Austin Hung ,  Tianshu Liu

    IPC: G06F1/28 ,  G06F11/30

    CPC classification number: G06F1/28 ,  G06F11/3062

    Abstract: Systems, apparatuses, and methods for dynamically estimating power losses in a computing system. A system management circuit tracks a state of a computing system and dynamically estimates power losses in the computing system based in part on the state. Based on the estimated power losses, power consumption of the computing system is estimated. In response to detecting reduced power losses in at least a portion of the computing system, the system management circuit is configured to increase a power-performance state of one or more circuits of the computing system while remaining within a power allocation limit of the computing system.

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