公开(公告)号：US20140017880A1

公开(公告)日：2014-01-16

申请号：US13938537

申请日：2013-07-10

申请人： Wei-Sheng LEI ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar

发明人： Wei-Sheng LEI ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/02019 ,  H01L21/027 ,  Y10T29/5124

摘要： Front side laser scribing and plasma etch are performed followed by back side grind to singulate integrated circuit chips (ICs). A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to advance a front of an etched trench partially through the semiconductor wafer thickness. The front side mask is removed, a backside grind tape applied to the front side, and a back side grind performed to reach the etched trench, thereby singulating the ICs.

公开(公告)号：US20140015109A1

公开(公告)日：2014-01-16

申请号：US13917973

申请日：2013-06-14

申请人： Wei-Sheng Lei ,  Brad Eaton ,  Aparna Iyer ,  Saravjeet Singh ,  Todd Egan ,  Ajay Kumar ,  Seshadri Ramaswami

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Aparna Iyer ,  Saravjeet Singh ,  Todd Egan ,  Ajay Kumar ,  Seshadri Ramaswami

IPC分类号： H01L21/78

CPC分类号： H01L23/32 ,  H01L21/463 ,  H01L21/47 ,  H01L21/475 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L21/82 ,  H01L27/04 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape.

摘要翻译： 描述了切割半导体晶片和输送单个模具的方法。 在一个示例中，在其上划分具有多个集成电路的晶片的方法包括将晶片切割成设置在切割带上方的多个单片模具。 该方法还涉及在切割胶带上方的多个分割模具之上和之间形成水溶性材料层。

公开(公告)号：US08568553B2

公开(公告)日：2013-10-29

申请号：US13045239

申请日：2011-03-10

申请人： Ajay Kumar ,  Madhavi R. Chandrachood ,  Richard Lewington ,  Darin Bivens ,  Amitabh Sabharwal ,  Sheeba J. Panayil ,  Alan Hiroshi Ouye

发明人： Ajay Kumar ,  Madhavi R. Chandrachood ,  Richard Lewington ,  Darin Bivens ,  Amitabh Sabharwal ,  Sheeba J. Panayil ,  Alan Hiroshi Ouye

IPC分类号： H01L21/306

CPC分类号： H01J37/32422 ,  H01J37/3244 ,  H01J37/32449

摘要： A method and apparatus for etching photomasks is provided herein. In one embodiment, the apparatus comprises a process chamber having a support pedestal adapted for receiving a photomask. An ion-neutral shield is disposed above the pedestal and a deflector plate assembly is provided above the ion-neutral shield. The deflector plate assembly defines a gas flow direction for process gases towards the ion-neutral shield, while the ion-neutral shield is used to establish a desired distribution of ion and neutral species in a plasma for etching the photomask.

摘要翻译： 本文提供了蚀刻光掩模的方法和设备。 在一个实施例中，该装置包括具有适于接收光掩模的支撑基座的处理室。 离子中性屏蔽设置在基座上方，偏转板组件设置在离子中性屏蔽层上方。 导流板组件限定了朝向离子中性屏蔽的工艺气体的气体流动方向，而离子中性屏蔽用于建立用于蚀刻光掩模的等离子体中的离子和中性物质的期望分布。

公开(公告)号：US08536910B2

公开(公告)日：2013-09-17

申请号：US13164457

申请日：2011-06-20

申请人： Krishnasawamy Nagaraj ,  Ajay Kumar

发明人： Krishnasawamy Nagaraj ,  Ajay Kumar

IPC分类号： H03L7/06

CPC分类号： H03L7/0891 ,  H03D13/00

摘要： A phased-locked loop (PLL) circuit which comprises a phase-frequency detector (PFD) configured to receive a reference signal, a voltage-controlled oscillator (VCO) configured to produce a VCO signal, and a divider configured to divide the VCO signal thereby producing a feedback signal based on the feedback signal not being locked to the reference signal. Based on the feedback signal not being locked to the reference signal, the PFD is configured to compare an edge of the reference signal with an edge of the feedback signal to produce an error signal. Based on the feedback signal being locked to the reference signal, the PFD is configured to compare the edge of the reference signal to an edge of the VCO signal to produce an error signal and the divider is configured to be disabled.

摘要翻译： 一种锁相环（PLL）电路，包括被配置为接收参考信号的相位频率检测器（PFD），被配置为产生VCO信号的压控振荡器（VCO）以及被配置为将VCO信号 从而基于未被锁定到参考信号的反馈信号产生反馈信号。 基于未被锁定到参考信号的反馈信号，PFD被配置为将参考信号的边沿与反馈信号的边沿进行比较以产生误差信号。 基于反馈信号被锁定到参考信号，PFD被配置为将参考信号的边沿与VCO信号的边沿进行比较以产生误差信号，并且分频器被配置为禁用。

公开(公告)号：US08476768B2

公开(公告)日：2013-07-02

申请号：US13170210

申请日：2011-06-28

申请人： Ajay Kumar ,  Sahil S. Dabare ,  Ajay K. Gaite ,  Shyam S. Gupta

发明人： Ajay Kumar ,  Sahil S. Dabare ,  Ajay K. Gaite ,  Shyam S. Gupta

IPC分类号： H01H79/00

CPC分类号： H01L23/50 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/06515 ,  H01L2224/16225 ,  H01L2224/1712 ,  H01L2224/48 ,  H01L2224/4912 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A system on a chip (SOC) includes a physical interface having first and second sets of interface pads. Interface pads from the first set are interleaved with interface pads from the second set. Additionally, the SOC is arranged for operation with a superset die having first and second personalities and has a physical interface with interface pads. The SOC uses a first number of interface pads in the first personality and a second number of interface pads in the second personality, where the first number is greater than the second number. A switch switches signals between the superset die and the physical interface and, in the second personality, switches signals to the physical interface so that interface pads in the second number of interface pads are interleaved with interface pads not in use in the second personality.

摘要翻译： 芯片上的系统（SOC）包括具有第一和第二组接口焊盘的物理接口。 来自第一组的接口焊盘与来自第二组的接口焊盘交错。 另外，SOC被配置为具有具有第一和第二个性的超级管芯的操作，并且具有与接口焊盘的物理接口。 SOC使用第一个人中的第一数量的接口焊盘和第二个人中的第二数量的接口焊盘，其中第一个数量大于第二个数量。 A开关在超级管芯和物理接口之间切换信号，并且在第二个性中将信号切换到物理接口，使得第二数量的接口焊盘中的接口焊盘与不在第二个性中使用的接口焊盘交错。

公开(公告)号：US20120322237A1

公开(公告)日：2012-12-20

申请号：US13161036

申请日：2011-06-15

申请人： Wei-Sheng Lei ,  Saravjeet Singh ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Ajay Kumar

发明人： Wei-Sheng Lei ,  Saravjeet Singh ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/78 ,  C23F1/08

CPC分类号： B23K26/40 ,  B23K26/0624 ,  B23K26/364 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/3081 ,  H01L21/31127 ,  H01L21/78

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The patterned mask is then separated from the singulated integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模。 面罩覆盖并保护集成电路。 用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以形成单独的集成电路。 然后将图案化掩模与单个集成电路分离。

公开(公告)号：US20120322236A1

公开(公告)日：2012-12-20

申请号：US13161026

申请日：2011-06-15

申请人： Wei-Sheng Lei ,  Saravjeet Singh ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Ajay Kumar

发明人： Wei-Sheng Lei ,  Saravjeet Singh ,  Madhava Rao Yalamanchili ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/82 ,  C23F1/08

CPC分类号： H01L21/3086 ,  B23K26/06 ,  B23K26/0622 ,  B23K26/0624 ,  B23K26/0626 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/67207 ,  H01L21/78

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a pulse train laser scribing process using multiple-pulse bursts to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模。 掩模由覆盖和保护集成电路的层组成。 使用多脉冲脉冲串的脉冲串激光划线方法对掩模进行构图，以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以对集成电路进行分离。

公开(公告)号：US20120322011A1

公开(公告)日：2012-12-20

申请号：US13455784

申请日：2012-04-25

申请人： Banqiu Wu ,  Ajay Kumar ,  Kartik Ramaswamy ,  Omkaram Nalamasu

发明人： Banqiu Wu ,  Ajay Kumar ,  Kartik Ramaswamy ,  Omkaram Nalamasu

IPC分类号： G03F7/36

CPC分类号： G03F7/36 ,  G03F7/40

摘要： The present invention provides methods and an apparatus controlling and minimizing process defects in a development process, and modifying line width roughness (LWR) of a photoresist layer after the development process, and maintaining good profile control during subsequent etching processes. In one embodiment, a method for forming features on a substrate includes developing and removing exposed areas in the photosensitive layer disposed on the substrate in the electron processing chamber by predominantly using electrons, removing contaminants from the substrate by predominantly using electrons, and etching the non-photosensitive polymer layer exposed by the developed photosensitive layer in the electron processing chamber by predominantly using electrons.

摘要翻译： 本发明提供了控制和最小化显影过程中的工艺缺陷的方法和装置，并且在显影过程之后修改光致抗蚀剂层的线宽粗糙度（LWR），并且在随后的蚀刻工艺期间保持良好的轮廓控制。 在一个实施例中，用于在衬底上形成特征的方法包括通过主要使用电子来显影和去除设置在电子处理室中的衬底上的感光层中的暴露区域，通过主要使用电子从衬底去除污染物， 通过主要使用电子在电子处理室中由显影的感光层曝光的光敏聚合物层。

公开(公告)号：US08293430B2

公开(公告)日：2012-10-23

申请号：US11044358

申请日：2005-01-27

申请人： Madhavi Chandrachood ,  Ajay Kumar ,  Wai-Fan Yau

发明人： Madhavi Chandrachood ,  Ajay Kumar ,  Wai-Fan Yau

IPC分类号： G03F1/00

CPC分类号： G03F1/32 ,  G03F1/54 ,  G03F1/80

摘要： Methods for fabricating a photomask are disclosed herein. In one embodiment, a method for fabricating a photomask includes providing a filmstack having a molybdenum layer and a light-shielding layer in a processing chamber, patterning a first resist layer on the light-shielding layer, etching the light-shielding layer using the first resist layer as an etch mask, and etching the molybdenum layer using the patterned light-shielding layer and the patterned first resist layer as a composite mask.

摘要翻译： 本文公开了制造光掩模的方法。 在一个实施例中，一种制造光掩模的方法包括在处理室中提供具有钼层和遮光层的薄膜层，对遮光层上的第一抗蚀剂层进行图案化，使用第一 抗蚀剂层作为蚀刻掩模，并且使用图案化遮光层和图案化的第一抗蚀剂层作为复合掩模蚀刻钼层。

公开(公告)号：US08084757B2

公开(公告)日：2011-12-27

申请号：US12015984

申请日：2008-01-17

申请人： Banqiu Wu ,  Ajay Kumar

发明人： Banqiu Wu ,  Ajay Kumar

IPC分类号： H05H1/00

CPC分类号： G03F7/70916 ,  G03F7/70858

摘要： Embodiments of the present invention provide methods and apparatus for removing debris particles using a stream of charged species. One embodiment of the present invention provides an apparatus for removing debris particles from a beam of radiation comprising a charged species source configured to dispense electrically charged species, and a collecting plate biased electrically opposite to the charged species from the charged species source, wherein the collecting plate and the charged species source are disposed on opposite sides of the beam of radiation, a stream of charged species from the charged species source to the collecting plate intersects the beam of radiation, the stream of charged species is configured to attach and remove debris particles from the beam of radiation by electrostatic force, and the collecting plate is configured to receive the charged species and the debris particles removed from the beam of radiation.

摘要翻译： 本发明的实施例提供了使用带电物质流去除碎屑颗粒的方法和装置。 本发明的一个实施例提供了一种用于从辐射束去除碎屑颗粒的装置，包括被配置成分配带电物质的带电物质源，以及与带电物质源电荷相反的收集板，其中收集 板和带电物质源设置在辐射束的相对侧上，从带电物质源到收集板的带电物流流与辐射束相交，带电物质流被配置为附着和去除碎屑颗粒 通过静电力从辐射束获得，并且收集板被配置为接收带电物质并且从辐射束去除碎屑颗粒。