利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

198 条记录 (耗时 0.027 秒)

    METHODS AND APPARATUS FOR PERFORMING MULTIPLE PHOTORESIST LAYER DEVELOPMENT AND ETCHING PROCESSES
    1.
    发明申请
    METHODS AND APPARATUS FOR PERFORMING MULTIPLE PHOTORESIST LAYER DEVELOPMENT AND ETCHING PROCESSES 有权
    用于执行多个光电层发展和蚀刻过程的方法和装置

    公开(公告)号：US20120322011A1

    公开(公告)日：2012-12-20

    申请号：US13455784

    申请日：2012-04-25

    申请人： Banqiu Wu ,  Ajay Kumar ,  Kartik Ramaswamy ,  Omkaram Nalamasu

    发明人： Banqiu Wu ,  Ajay Kumar ,  Kartik Ramaswamy ,  Omkaram Nalamasu

    IPC分类号： G03F7/36

    CPC分类号： G03F7/36 ,  G03F7/40

    摘要： The present invention provides methods and an apparatus controlling and minimizing process defects in a development process, and modifying line width roughness (LWR) of a photoresist layer after the development process, and maintaining good profile control during subsequent etching processes. In one embodiment, a method for forming features on a substrate includes developing and removing exposed areas in the photosensitive layer disposed on the substrate in the electron processing chamber by predominantly using electrons, removing contaminants from the substrate by predominantly using electrons, and etching the non-photosensitive polymer layer exposed by the developed photosensitive layer in the electron processing chamber by predominantly using electrons.

    摘要翻译： 本发明提供了控制和最小化显影过程中的工艺缺陷的方法和装置，并且在显影过程之后修改光致抗蚀剂层的线宽粗糙度（LWR），并且在随后的蚀刻工艺期间保持良好的轮廓控制。 在一个实施例中，用于在衬底上形成特征的方法包括通过主要使用电子来显影和去除设置在电子处理室中的衬底上的感光层中的暴露区域，通过主要使用电子从衬底去除污染物， 通过主要使用电子在电子处理室中由显影的感光层曝光的光敏聚合物层。

    Methods and apparatus for performing multiple photoresist layer development and etching processes
    2.
    发明授权
    Methods and apparatus for performing multiple photoresist layer development and etching processes 有权
    用于进行多个光致抗蚀剂层显影和蚀刻工艺的方法和装置

    公开(公告)号：US08709706B2

    公开(公告)日：2014-04-29

    申请号：US13455784

    申请日：2012-04-25

    申请人： Banqiu Wu ,  Ajay Kumar ,  Kartik Ramaswamy ,  Omkaram Nalamasu

    发明人： Banqiu Wu ,  Ajay Kumar ,  Kartik Ramaswamy ,  Omkaram Nalamasu

    IPC分类号： G03F7/26

    CPC分类号： G03F7/36 ,  G03F7/40

    摘要： The present invention provides methods and an apparatus controlling and minimizing process defects in a development process, and modifying line width roughness (LWR) of a photoresist layer after the development process, and maintaining good profile control during subsequent etching processes. In one embodiment, a method for forming features on a substrate includes developing and removing exposed areas in the photosensitive layer disposed on the substrate in the electron processing chamber by predominantly using electrons, removing contaminants from the substrate by predominantly using electrons, and etching the non-photosensitive polymer layer exposed by the developed photosensitive layer in the electron processing chamber by predominantly using electrons.

    摘要翻译： 本发明提供了控制和最小化显影过程中的工艺缺陷的方法和装置，并且在显影过程之后修改光致抗蚀剂层的线宽粗糙度（LWR），并且在随后的蚀刻工艺期间保持良好的轮廓控制。 在一个实施例中，用于在衬底上形成特征的方法包括通过主要使用电子来显影和去除设置在电子处理室中的衬底上的感光层中的暴露区域，通过主要使用电子从衬底去除污染物， 通过主要使用电子在电子处理室中由显影的感光层曝光的光敏聚合物层。

    METHODS AND APPARATUS FOR CONTROLLING PHOTORESIST LINE WIDTH ROUGHNESS WITH ENHANCED ELECTRON SPIN CONTROL
    3.
    发明申请
    METHODS AND APPARATUS FOR CONTROLLING PHOTORESIST LINE WIDTH ROUGHNESS WITH ENHANCED ELECTRON SPIN CONTROL 审中-公开
    用于控制光电子束宽度粗糙度的方法和装置，具有增强的电子旋转控制

    公开(公告)号：US20120318773A1

    公开(公告)日：2012-12-20

    申请号：US13455753

    申请日：2012-04-25

    申请人： Banqiu Wu ,  Ajay Kumar ,  Kartik Ramaswamy ,  Omkaram Nalamasu

    发明人： Banqiu Wu ,  Ajay Kumar ,  Kartik Ramaswamy ,  Omkaram Nalamasu

    IPC分类号： B44C1/22 ,  B05C13/00

    CPC分类号： H01J37/32669 ,  H01J37/32009 ,  H01J37/32422 ,  H01J37/3244 ,  H01L21/0273 ,  H01L21/31144

    摘要： The present invention provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.

    摘要翻译： 本发明提供了通过增强的电子纺丝控制来控制和修改光致抗蚀剂层的线宽粗糙度（LWR）的方法和装置。 在一个实施例中，用于控制设置在基板上的光致抗蚀剂层的线宽粗糙度的装置包括处理室，该处理室具有室主体，该室主体具有限定内部处理区域的顶壁，侧壁和底壁， 处理室的内部处理区域和设置在处理室中的等离子体发生器源，其可操作以主要向内部处理区域提供电子束源。

    Plasma reactor with uniform process rate distribution by improved RF ground return path
    10.
    发明授权
    Plasma reactor with uniform process rate distribution by improved RF ground return path 有权
    等离子体反应器具有均匀的加工速率分布，通过改进的射频接地回路

    公开(公告)号：US08360003B2

    公开(公告)日：2013-01-29

    申请号：US12501966

    申请日：2009-07-13

    申请人： Andrew Nguyen ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Samer Banna ,  Anchel Sheyner ,  Valentin N. Todorow

    发明人： Andrew Nguyen ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Samer Banna ,  Anchel Sheyner ,  Valentin N. Todorow

    IPC分类号： C23C16/00 ,  H01L21/306

    CPC分类号： H01J37/16 ,  H01J37/321 ,  H01J37/32623 ,  H01J37/32633 ,  H01J37/32642 ,  H01L31/18

    摘要： In a plasma reactor having an RF plasma source power applicator at its ceiling, an integrally formed grid liner includes a radially extending plasma confinement ring and an axially extending side wall liner. The plasma confinement ring extends radially outwardly near the plane of a workpiece support surface from a pedestal side wall, and includes an annular array of radial slots, each of the slots having a narrow width corresponding to an ion collision mean free path length of a plasma in the chamber. The side wall liner covers an interior surface of the chamber side wall and extends axially from a height near a height of said workpiece support surface to the chamber ceiling.

    摘要翻译： 在其顶部具有RF等离子体源功率施加器的等离子体反应器中，整体形成的栅格衬套包括径向延伸的等离子体限制环和轴向延伸的侧壁衬套。 等离子体约束环从基座侧壁在工件支撑表面的平面附近径向向外延伸，并且包括径向槽的环形阵列，每个槽具有对应于等离子体的离子碰撞平均自由路径长度的窄宽度 在房间里 侧壁衬套覆盖室侧壁的内表面并且从靠近所述工件支撑表面的高度的高度轴向延伸到室顶部。