公开(公告)号：US08008213B2

公开(公告)日：2011-08-30

申请号：US12285220

申请日：2008-09-30

申请人： Li Xiao ,  Jingyan Zhang ,  Huicai Zhong

发明人： Li Xiao ,  Jingyan Zhang ,  Huicai Zhong

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L27/2409 ,  H01L27/101 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/16

摘要： A method of making a device includes forming at least one anodizable metal layer over at least one of an electrode or a semiconductor device, forming a plurality of pores in the anodizable metal layer by anodization of the anodizable metal layer to expose a portion of the electrode or semiconductor device, and filling at least one pore with a rewritable material such that at least some of the rewritable material is in electrical contact with the electrode or semiconductor device.

摘要翻译： 一种制造器件的方法包括在电极或半导体器件中的至少一个上形成至少一个阳极氧化金属层，通过阳极氧化阳极氧化金属层在阳极氧化金属层中形成多个孔以暴露电极的一部分 或半导体器件，并且用可重写材料填充至少一个孔，使得至少一些可重写材料与电极或半导体器件电接触。

公开(公告)号：US07569892B2

公开(公告)日：2009-08-04

申请号：US11776584

申请日：2007-07-12

申请人： Huilong Zhu ,  Huicai Zhong ,  Effendi Leobandung

发明人： Huilong Zhu ,  Huicai Zhong ,  Effendi Leobandung

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/7843 ,  Y10S438/938

摘要： A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the first polarity type device are removed.

摘要翻译： 用于形成用于CMOS器件的自对准双应力衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一类型应力层，并在第一氮化物层上形成牺牲层。 第一类型应力层和第二极性类型器件上的牺牲层的部分被图案化和去除。 第二类型应力层形成在第二极性类型器件上方，并且在第一极性类型器件上方的牺牲层的剩余部分上，以使得第二类型应力层在水平表面上比在侧壁上形成更大的厚度 表面。 除去侧壁表面上的第二类型应力衬垫的部分，并且去除第一极性类型装置上的第二类型应力衬垫的部分。

公开(公告)号：US07456058B1

公开(公告)日：2008-11-25

申请号：US11231405

申请日：2005-09-21

申请人： Igor Peidous ,  Linda R. Black ,  Huicai Zhong

发明人： Igor Peidous ,  Linda R. Black ,  Huicai Zhong

IPC分类号： H01L21/338

CPC分类号： H01L21/28114 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/7843 ,  H01L29/7845

摘要： Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal portion. The vertical portion overlies a channel region in an underlying substrate and has a first width; the horizontal portion has a second greater width. A tensile stressed film is formed overlying the second horizontal portion, and a material having a second Young's modulus less than the first Young's modulus fills the space below the second horizontal portion. The tensile stressed film imparts a stress on the horizontal portion of the gate electrode and this stress is transmitted through the vertical portion to the channel of the device. The stress imparted to the channel is amplified by the ratio of the second width to the first width.

摘要翻译： 提供了强调MOS器件及其制造方法。 应力MOS器件包括由具有第一杨氏模量的材料形成的T形栅电极。 T形栅电极包括第一垂直部分和第二水平部分。 垂直部分覆盖在下面的衬底中的沟道区域并且具有第一宽度; 水平部分具有第二较大的宽度。 形成覆盖在第二水平部分上的拉伸应力膜，并且具有小于第一杨氏模量的第二杨氏模量的材料填充第二水平部分下方的空间。 拉伸应力膜在栅电极的水平部分施加应力，并且该应力通过垂直部分传输到器件的通道。 施加到通道的应力通过第二宽度与第一宽度的比率被放大。

公开(公告)号：US20080204200A1

公开(公告)日：2008-08-28

申请号：US11710673

申请日：2007-02-26

申请人： Huilong Zhu ,  Huicai Zhong

发明人： Huilong Zhu ,  Huicai Zhong

IPC分类号： G01S1/02

CPC分类号： G01S5/02 ,  G01S5/0221 ,  G01S13/878

摘要： Methods and systems with one or more mobile transceivers to locate position of radio frequency identification (RFID) tags via radio frequency (RF) technology are disclosed. The systems called RF Locator (RFL) include at least one mobile RF transceiver and other functional components such as, a globe positioning system (GPS), a processor, and a display. Information of space positions, times and physical characteristics related to RF signals are collected sequentially by the mobile transceiver(s) during RFID tag locating process. The processor calculates the location of the RFID tag by using the collected information. Two methods to determine the location of the RFID tag are disclosed in this invention. The first method is to utilize the information of space positions and times. The second method is to use the information of space positions and RF signal characteristics.

摘要翻译： 公开了具有一个或多个移动收发器以通过射频（RF）技术定位射频识别（RFID）标签的位置的方法和系统。 称为RF定位器（RFL）的系统包括至少一个移动RF收发器和诸如球体定位系统（GPS），处理器和显示器的其他功能组件。 与RFID射频信号相关的空间位置，时间和物理特性的信息在RFID标签定位过程中由移动收发机依次收集。 处理器使用收集的信息计算RFID标签的位置。 在本发明中公开了确定RFID标签位置的两种方法。 第一种方法是利用空间位置和时间的信息。 第二种方法是使用空间位置和RF信号特征的信息。

公开(公告)号：US20080012019A1

公开(公告)日：2008-01-17

申请号：US11776584

申请日：2007-07-12

申请人： Huilong Zhu ,  Huicai Zhong ,  Effendi Leobandung

发明人： Huilong Zhu ,  Huicai Zhong ,  Effendi Leobandung

IPC分类号： H01L27/108 ,  H01L21/31

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/7843 ,  Y10S438/938

摘要： A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the first polarity type device are removed.

摘要翻译： 用于形成用于CMOS器件的自对准双应力衬垫的方法包括在第一极性类型器件和第二极性器件上形成第一类型应力层，并在第一氮化物层上形成牺牲层。 第一类型应力层和第二极性类型器件上的牺牲层的部分被图案化和去除。 第二类型应力层形成在第二极性类型器件上方，并且在第一极性类型器件上方的牺牲层的剩余部分上，以使得第二类型应力层在水平表面上比在侧壁上形成更大的厚度 表面。 除去侧壁表面上的第二类型应力衬垫的部分，并且去除第一极性类型装置上的第二类型应力衬垫的部分。

公开(公告)号：US20060281270A1

公开(公告)日：2006-12-14

申请号：US11147383

申请日：2005-06-08

申请人： Johannes Meer ,  Huicai Zhong

发明人： Johannes Meer ,  Huicai Zhong

IPC分类号： H01L21/336

CPC分类号： H01L29/6653 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/7834

摘要： A method for forming raised source and drain regions in a semiconductor manufacturing process employs double disposable spacers. A deposited oxide is provided between the first and second disposable spacers, and serves to protect the gate electrode, first disposable spacers and a cap layer during the dry etching of the larger, second disposable spacers. Mouse ears are thereby prevented, while the use of a second disposable spacer avoids shadow-effects during halo ion-implants.

摘要翻译： 在半导体制造工艺中形成凸起的源极和漏极区域的方法使用双重一次性间隔物。 沉积的氧化物设置在第一和第二一次性间隔件之间，并且用于在较大的第二一次性间隔件的干蚀刻期间保护栅电极，第一一次性间隔件和盖层。 从而防止了鼠耳朵，而使用第二个一次性间隔件避免了晕圈离子注入过程中的阴影效应。

公开(公告)号：US09653358B2

公开(公告)日：2017-05-16

申请号：US13133061

申请日：2011-02-25

申请人： Huicai Zhong ,  Qingqing Liang

发明人： Huicai Zhong ,  Qingqing Liang

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823412 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7848

摘要： The present invention presents a method for manufacturing a semiconductor device structure as well as the semiconductor device structure. Said method comprises: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a channel region embedded in the semiconductor substrate; and forming a gate stack stripe on the channel region. Said method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate. By means of forming the source/drain regions in a self-aligned manner before forming the channel region and the gate stack, said method achieves the advantageous effects of the replacement gate process without using a dummy gate, thereby simplifying the process and reducing the cost.

公开(公告)号：US09312361B2

公开(公告)日：2016-04-12

申请号：US13578872

申请日：2012-05-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

发明人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer.

摘要翻译： 公开了半导体装置及其制造方法。 在一个实施例中，该方法包括：在衬底上形成第一屏蔽层，并在第一屏蔽层的侧壁上形成第一间隔物; 用第一屏蔽层和第一间隔件作为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并移除所述第一屏蔽层; 用第二屏蔽层和第一间隔物作为掩模形成源区和漏区中的另一个; 去除所述第一间隔物的至少一部分; 以及形成栅极电介质层，以及在所述第二屏蔽层的侧壁或所述第一间隔物的剩余部分的侧壁上形成间隔物形式的栅极导体。

公开(公告)号：US09147745B2

公开(公告)日：2015-09-29

申请号：US13981808

申请日：2012-07-24

申请人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong ,  Hao Wu

发明人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong ,  Hao Wu

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28 ,  H01L29/51

CPC分类号： H01L29/66477 ,  H01L21/2815 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78639 ,  H01L29/78654

摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.

摘要翻译： 公开了半导体装置及其制造方法。 在一个实施例中，该方法包括：在衬底上顺序形成牺牲层和半导体层; 在所述半导体层上形成第一覆盖层; 形成以第一覆盖层为掩模延伸到基板的开口; 通过所述开口选择性地去除所述牺牲层的至少一部分，并且由于去除所述牺牲层而在绝缘材料中填充绝缘材料; 在开口中形成源极和漏极区域之一; 在所述基板上形成第二覆盖层; 以第二覆盖层为掩模形成源区和漏区中的另一个; 去除所述第二覆盖层的一部分; 以及形成栅极电介质层，并且在所述第二覆盖层的剩余部分的侧壁上形成隔板形式的栅极导体。

公开(公告)号：US09064954B2

公开(公告)日：2015-06-23

申请号：US13623567

申请日：2012-09-20

申请人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

发明人： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7816 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. The method further includes removing a portion of the second shielding layer which is next to the other of the source and drain regions. The method further includes forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.

摘要翻译： 公开了半导体装置及其制造方法。 在一个实施例中，一种方法包括在衬底上形成第一屏蔽层。 该方法还包括以第一屏蔽层为掩模形成应力的源区和漏区中的一个。 该方法还包括在衬底上形成第二屏蔽层，并且以第二屏蔽层作为掩模形成源区和漏区中的另一个。 该方法还包括去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。 该方法还包括形成栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。