公开(公告)号：US07471244B2

公开(公告)日：2008-12-30

申请号：US11552231

申请日：2006-10-24

Applicant: Jim Omura ,  Matthew Rabinowitz ,  James J. Spilker, Jr. ,  Ju-Yong Do ,  Andy Lee

Inventor： Jim Omura ,  Matthew Rabinowitz ,  James J. Spilker, Jr. ,  Ju-Yong Do ,  Andy Lee

IPC: G01S3/02

CPC classification number: G01S5/0036 ,  G01S5/0054 ,  G01S5/0081 ,  G01S5/021 ,  G01S5/0215 ,  G01S5/0221 ,  G01S5/14 ,  G01S5/145

Abstract: Apparatus having corresponding methods comprises a reference clock; a receiver to receive a wireless television signal, wherein the wireless television signal is transmitted by a television transmitter according to a transmitter clock; and a clock offset unit to determine a clock offset between the reference clock and the transmitter clock based on the wireless television signal.

Abstract translation: 具有相应方法的装置包括参考时钟; 接收器，用于接收无线电视信号，其中所述无线电视信号由电视发射机根据发射机时钟发射; 以及时钟偏移单元，用于基于无线电视信号确定参考时钟和发射机时钟之间的时钟偏移。

公开(公告)号：US20080040886A1

公开(公告)日：2008-02-21

申请号：US11698535

申请日：2007-01-26

Applicant: Robert Arnold ,  Dhananjay Bhatt ,  Nicholas Welche ,  Andy Lee

Inventor： Robert Arnold ,  Dhananjay Bhatt ,  Nicholas Welche ,  Andy Lee

IPC: F16C33/10

CPC classification number: F16C33/201 ,  B64C9/16 ,  F16C23/045 ,  F16C33/102 ,  F16C33/1065 ,  F16C33/12 ,  F16C2326/43 ,  Y02T50/44 ,  Y10T16/5377

Abstract: A spherical plain bearing has an outer ring having a concave first bearing surface and an inner ring having a convex second bearing surface slidably disposed to the first bearing surface. The inner ring member also has a third bearing surface for engaging a pin to be mounted in the bearing. At least one bearing surface has a lubrication groove, and one of the outer ring and the inner ring is made from 440 stainless steel while the other is made from a precipitation-hardened martensitic stainless steel. Alternatively, the outer ring and the inner ring may be made from steel and a copper-beryllium alloy. In yet another alternative, the bearing need not have a lubrication groove, but may have a lubrication liner on the third bearing surface. A dropped hinge mechanism for a flap on a fixed wing aircraft has a hinge that includes such a bearing.

Abstract translation: 球面滑动轴承具有外环，该外圈具有凹形的第一支承表面和具有可滑动地设置在第一支承表面上的凸形的第二支承表面的内圈。 内环构件还具有用于接合待安装在轴承中的销的第三支承表面。 至少一个轴承表面具有润滑槽，外环和内圈中的一个由440个不锈钢制成，另一个由沉淀硬化的马氏体不锈钢制成。 或者，外圈和内圈可以由钢和铜 - 铍合金制成。 在另一替代方案中，轴承不需要具有润滑槽，而是可以在第三轴承表面上具有润滑衬垫。 用于固定翼飞机上的翼片的下落铰链机构具有包括这种轴承的铰链。

公开(公告)号：US20070040576A1

公开(公告)日：2007-02-22

申请号：US11316390

申请日：2005-12-22

Applicant: David Lewis ,  Christopher Lane ,  Sarathy Sribhashyam ,  Srinivas Perisetty ,  Tim Vanderhoek ,  Vaughn Betz ,  Thomas Wong ,  Andy Lee

Inventor： David Lewis ,  Christopher Lane ,  Sarathy Sribhashyam ,  Srinivas Perisetty ,  Tim Vanderhoek ,  Vaughn Betz ,  Thomas Wong ,  Andy Lee

IPC: H03K19/177

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  H03K19/17784

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract translation: 可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。 控制电路耦合到非易失性存储器和配置存储器。 一组电压从控制电路的输出导出，并被应用于PLD内的电路。

公开(公告)号：US06965249B2

公开(公告)日：2005-11-15

申请号：US10159581

申请日：2002-05-30

Applicant: Christopher Lane ,  Ketan Zaveri ,  Hyun Yi ,  Giles Powell ,  Paul Leventis ,  David Jefferson ,  David Lewis ,  Triet Nguyen ,  Vikram Santurkar ,  Michael Chan ,  Andy Lee ,  Brian Johnson ,  David Cashman

Inventor： Christopher Lane ,  Ketan Zaveri ,  Hyun Yi ,  Giles Powell ,  Paul Leventis ,  David Jefferson ,  David Lewis ,  Triet Nguyen ,  Vikram Santurkar ,  Michael Chan ,  Andy Lee ,  Brian Johnson ,  David Cashman

IPC: H01L21/82 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/17736 ,  H03K19/17744

Abstract: A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

Abstract translation: 可编程逻辑器件和相关方法提供有可修复区域。 在一个方面，一般布线互连线在可修复区域内被分段。 在另一方面，提供IO总线线路和相关电路，其适应交错分段结构中的冗余。 在另一方面，特定逻辑区域之间的专用路由架构适应移位以限定和利用可修复区域。 在本发明的方面的几个示例性实施例的上下文中示出和描述了其它方面的原理。

公开(公告)号：US20050127944A1

公开(公告)日：2005-06-16

申请号：US11050111

申请日：2005-02-02

Applicant: David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

Inventor： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US06842040B1

公开(公告)日：2005-01-11

申请号：US10319329

申请日：2002-12-13

Applicant: Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

Inventor： Wanli Chang ,  Andy Lee ,  Cameron McClintock ,  Richard Cliff ,  Richard Yen-Hsiang Chang

IPC: H03K5/151 ,  H03K19/017 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K5/151 ,  H03K19/01721 ,  H03K19/17784

Abstract: At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.

Abstract translation: 可编程逻辑器件（“PLD”）上的至少一些互连信号通过使用差分驱动器电路的差分信号来将差分信号施加到延伸到差分接收器电路的一对导体。 这种差分互连信令有助于PLD在较低的电源电压下令人满意地工作。 每个差分信号对中的导体可以以不同的间隔彼此交叉，以便有助于减少相邻和并行信令路径之间的电容耦合的不利影响。

公开(公告)号：US06700717B2

公开(公告)日：2004-03-02

申请号：US10426445

申请日：2003-04-29

Applicant: Andy Lee

Inventor： Andy Lee

IPC: G02B2608

CPC classification number: H04N1/04 ,  H04N2201/0444 ,  H04N2201/0446 ,  Y10T74/18704

Abstract: The present invention provides a locking apparatus for switching between a lock state and an unlock state of a sliding device in a system. The system has a plug and a socket. The sliding device has a shaft. The locking apparatus has a sliding member, a spring, a hook, and a connecting member. The hook has an end part and a bending portion for locking the shaft. When the plug is plugged into the socket, the locking apparatus unlocks the shaft. When the plug is pulled out from the socket, the locking apparatus locks the shaft.

Abstract translation: 本发明提供了一种用于在系统中的滑动装置的锁定状态和解锁状态之间切换的锁定装置。 系统有一个插头和一个插座。 滑动装置具有轴。 锁定装置具有滑动构件，弹簧，钩和连接构件。 钩具有用于锁定轴的端部和弯曲部。 当插头插入插座时，锁定装置解锁轴。 当插头从插座拔出时，锁定装置锁定轴。

公开(公告)号：US06551065B2

公开(公告)日：2003-04-22

申请号：US09875894

申请日：2001-06-08

Applicant: Andy Lee

Inventor： Andy Lee

IPC: F04B4910

CPC classification number: F04D27/008

Abstract: A device to protect fans from overheating and overloading with driving current. The fan protection device of the present invention monitors the temperature and current change of the operating fan. When the temperature or the current float surpasses a predetermined value, the protection device cuts off the fan's power supply and avoids damage to the unit.

公开(公告)号：US6128215A

公开(公告)日：2000-10-03

申请号：US38123

申请日：1998-03-11

Applicant: Andy Lee

Inventor： Andy Lee

IPC: G11C11/41 ,  G11C7/20 ,  G11C11/40

CPC classification number: G11C7/20

Abstract: A static random access memory ("SRAM") that is especially suitable for such uses as inclusion on a programmable logic device to provide programmable control of the configuration of that device. The SRAM includes a plurality of SRAM cells, all of which are simultaneously cleared to a first of two logic states by application of a second of the two logic states to clear terminals of the cells. Any cell that needs to be programmed to the second of the two logic states is thereafter specifically addressed and a data signal thereby applied which programs the cell to the second logic state. The cells are preferably constructed so that they are programmed to the second logic state by application of a data signal having the first logic state. Even a very small unipolar MOS pass gate transistor can therefore be used as the addressable path through which the data signal is applied. The memory may also include circuitry for verifying the contents of each cell via the data input terminal of the cell.

公开(公告)号：US20120261738A1

公开(公告)日：2012-10-18

申请号：US13538438

申请日：2012-06-29

Applicant: Dustin Do ,  Andy Lee ,  Giles V. Powell ,  Bradley Jensen ,  Swee Aun Lau ,  Wuu-Cherng Lin ,  Thomas H. White

Inventor： Dustin Do ,  Andy Lee ,  Giles V. Powell ,  Bradley Jensen ,  Swee Aun Lau ,  Wuu-Cherng Lin ,  Thomas H. White

IPC: H01L29/788

CPC classification number: H01L27/0207 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878

Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Abstract translation: 公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带而获得较低的空间要求。