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    GRAPHICS PROCESSING UNIT PROVIDING THERMAL CONTROL VIA RENDER QUALITY DEGRADATION
    24.
    发明申请
    GRAPHICS PROCESSING UNIT PROVIDING THERMAL CONTROL VIA RENDER QUALITY DEGRADATION 审中-公开
    图形处理单元通过渲染质量降级提供热控制

    公开(公告)号：US20170061570A1

    公开(公告)日：2017-03-02

    申请号：US15248499

    申请日：2016-08-26

    Applicant: Apple, Inc.

    Inventor： Gokhan Avkarogullari ,  Jason P. Jane ,  Alex Kan

    IPC: G06T1/20 ,  G06T11/00 ,  G06F1/32 ,  G06T7/40

    CPC classification number: G06T1/20 ,  G06F1/3215 ,  G06F1/325

    Abstract: Power management techniques are disclosed for a graphics processing unit (GPU) in which the GPU determines whether it is operating outside an operational limit and, when the GPU is operating outside the operational limit, the GPU alters performance of an operation to be performed texture processor within the GPU to reduce complexity of the operation. Otherwise, the GPU may perform the texture processing operation at its default complexity. These techniques provide a degree of power control not available in other techniques.

    Abstract translation: 电源管理技术被公开用于图形处理单元（GPU），其中GPU确定其是否在操作限制之外操作，并且当GPU在操作限制之外操作时，GPU改变要执行的操作的性能纹理处理器 在GPU内降低操作的复杂性。 否则，GPU可以以其默认的复杂度执行纹理处理操作。 这些技术提供了在其他技术中不可用的一定程度的功率控制。

    Graphics Pipeline State Object And Model
    25.
    发明申请
    Graphics Pipeline State Object And Model 审中-公开
    图形管道状态对象和模型

    公开(公告)号：US20150348224A1

    公开(公告)日：2015-12-03

    申请号：US14501933

    申请日：2014-09-30

    Applicant: Apple Inc.

    Inventor： Gokhan Avkarogullari ,  Eric O. Sunalp ,  Richard W. Schreyer ,  Alexander K. Kan

    IPC: G06T1/20 ,  G06F9/45 ,  G06T15/80

    CPC classification number: G06T1/20 ,  G06F3/14 ,  G06F8/47 ,  G06T15/80 ,  G06T2200/28

    Abstract: An innovative GPU framework and related APIs present more accurate representations of the target hardware so that the distinctions between the fixed-function and programmable features of the GPU are perceived by a developer. This permits a program and/or a graphics object generated or manipulated by the program to be understood as not just code, but machine states that are associated with the code. When such an object is defined, the definitional components requiring programmable GPU features can be compiled only once and reused repeatedly as needed. Similarly, when a state change is made, the state changes correspond to the state changes made on the hardware. Additionally, the creation of these immutable objects prevents a developer from inadvertently changing portions of the program or object that cause it to behave differently than intended.

    Abstract translation: 创新的GPU框架和相关的API提供目标硬件的更准确的表示，以便GPU的固定功能和可编程功能之间的区别被开发人员所感知。 这允许由程序生成或操纵的程序和/或图形对象被理解为不仅仅是代码，而是与代码相关联的机器状态。 当定义这样的对象时，需要可编程GPU特征的定义组件只能编译一次，并根据需要重复使用。 类似地，当进行状态改变时，状态改变对应于在硬件上进行的状态改变。 另外，这些不可变对象的创建可以防止开发人员无意中更改程序或对象的部分内容，导致其行为与预期的不同。

    DISPLAY DRIVING ARCHITECTURES
    26.
    发明申请
    DISPLAY DRIVING ARCHITECTURES 审中-公开
    显示驱动架构

    公开(公告)号：US20150138215A1

    公开(公告)日：2015-05-21

    申请号：US14601070

    申请日：2015-01-20

    Applicant: Apple Inc.

    Inventor： Gokhan Avkarogullari ,  John Harper ,  Joshua H. Shaffer ,  Roberto G. Yepez

    IPC: G06T1/20 ,  G06T5/00 ,  G06T11/60 ,  G06F3/14 ,  G06T3/40 ,  G06T11/00

    CPC classification number: G06T1/20 ,  G06F3/1431 ,  G06F3/1438 ,  G06T3/40 ,  G06T5/009 ,  G06T11/001 ,  G06T11/60 ,  G09G5/006 ,  G09G2330/021 ,  G09G2340/0407 ,  G09G2340/06 ,  G09G2340/125 ,  G09G2370/04 ,  G09G2370/10 ,  G09G2370/12

    Abstract: A display driving architecture that can include two graphics pipelines with an optional connection between them to provide a mirrored mode. In one embodiment, one of the two pipelines can be automatically configured (e.g. routed in one of a plurality of ways, such as routing to do color conversion) based upon the type of cable that is coupled to a connector of the one pipeline. In another embodiment, a connection of a cable can cause display information (e.g. resolutions of an external display) to be provided to an application which can select a display mode while one of the graphics pipelines is kept in a low power state.

    Abstract translation: 显示驱动体系结构，可以包括两个图形流水线与它们之间的可选连接，以提供镜像模式。 在一个实施例中，基于耦合到一个管道的连接器的电缆的类型，两个管线中的一个可以被自动配置（例如，以多种方式之一路由，例如路由以进行颜色转换）。 在另一个实施例中，电缆的连接可以使显示信息（例如，外部显示器的分辨率）被提供给可以在图形管线中的一个保持在低功率状态的同时选择显示模式的应用。

    Displays with variable frame rates
    27.
    发明授权
    Displays with variable frame rates 有权

    公开(公告)号：US12131719B2

    公开(公告)日：2024-10-29

    申请号：US17887222

    申请日：2022-08-12

    Applicant: Apple Inc.

    Inventor： Wanqing Xin ,  Mehmet N Agaoglu ,  Gokhan Avkarogullari ,  Jenny Hu ,  Alexander K Kan ,  Yuhui Li ,  James R Montgomerie ,  Andrey Pokrovskiy ,  Yingying Tang ,  Chaohao Wang

    IPC: G09G5/36

    CPC classification number: G09G5/363 ,  G09G2340/0435 ,  G09G2370/04 ,  G09G2370/22

    Abstract: An electronic device may include a display. Control circuitry may operate the display at different frame rates such as 60 Hz, 80 Hz, and 120 Hz. The control circuitry may determine which frame rate to use based on a speed of animation on the display and based on a type of animation on the display. To mitigate the appearance of judder as the display frame rate changes, the control circuitry may implement techniques such as hysteresis (e.g., windows of tolerance around speed thresholds to ensure that the display frame rate does not change too frequently as a result of noise), speed thresholds that are based on a user perception study, consistent latency between touch input detection and corresponding display output across different frame rates (e.g., using a fixed touch scan rate that is independent of frame duration), and animation-specific speed thresholds for triggering frame rate changes.

    Graphics Surface Addressing
    28.
    发明申请
    Graphics Surface Addressing 有权

    公开(公告)号：US20210074053A1

    公开(公告)日：2021-03-11

    申请号：US16953021

    申请日：2020-11-19

    Applicant: Apple Inc.

    Inventor： Anthony P. DeLaurier ,  Michael J. Swift ,  Michal Valient ,  Robert S. Hartog ,  Tyson J. Bergland ,  Gokhan Avkarogullari

    IPC: G06T15/04 ,  G06T1/60 ,  G06F9/38 ,  G06T11/00 ,  G06F12/1009 ,  G06F9/50 ,  G06T15/00 ,  G06F12/0811

    Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

    Graphics hardware driven pause for quality of service adjustment
    29.
    发明授权
    Graphics hardware driven pause for quality of service adjustment 有权

    公开(公告)号：US10795730B2

    公开(公告)日：2020-10-06

    申请号：US16145573

    申请日：2018-09-28

    Applicant: Apple Inc.

    Inventor： Kutty Banerjee ,  Benjamin Bowman ,  Terence M. Potter ,  Tatsuya Iwamoto ,  Gokhan Avkarogullari

    IPC: G06F9/50 ,  G06F9/38 ,  G06F9/54

    Abstract: In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.

    Task Execution on a Graphics Processor Using Indirect Argument Buffers
    30.
    发明申请
    Task Execution on a Graphics Processor Using Indirect Argument Buffers 审中-公开

    公开(公告)号：US20200242726A1

    公开(公告)日：2020-07-30

    申请号：US16850101

    申请日：2020-04-16

    Applicant: Apple Inc.

    Inventor： Michal Valient ,  Sean P. James ,  Gokhan Avkarogullari ,  Alexander K. Kan ,  Michael Imbrogno

    IPC: G06T1/60 ,  G06F9/448 ,  G09G5/36 ,  G06T15/04 ,  G06F3/14 ,  G06T15/00 ,  G06T1/20

    Abstract: The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processer in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processer in response to passing the data structure to the second programming interface command.

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