公开(公告)号：US12141016B2

公开(公告)日：2024-11-12

申请号：US18476547

申请日：2023-09-28

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/32 ,  G06F1/3228 ,  G06F1/3287 ,  H04B17/318

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US11875427B2

公开(公告)日：2024-01-16

申请号：US17473754

申请日：2021-09-13

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Christopher P. Tann ,  Rohit K. Gupta

IPC: G06T1/60 ,  G06F12/0895 ,  G06F12/0873 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/0873 ,  G06F12/0895 ,  G06T1/20 ,  G06F2212/1024 ,  G06F2212/401 ,  G06F2212/455

Abstract: An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to generate the processed image data based on input image data and previously determined data stored in memory. The image processing circuitry may also operate according to real-time computing constraints. Cache memory may store the previously determined data in a provisioned section of the cache memory allotted to the image processing circuitry. Additionally, a controller may manage reading and writing of the previously determined data to the provisioned section of the cache memory.

公开(公告)号：US20230081746A1

公开(公告)日：2023-03-16

申请号：US17473754

申请日：2021-09-13

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Christopher P. Tann ,  Rohit K. Gupta

IPC: G06T1/60 ,  G06F12/0895 ,  G06F12/0873 ,  G06T1/20

Abstract: An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to generate the processed image data based on input image data and previously determined data stored in memory. The image processing circuitry may also operate according to real-time computing constraints. Cache memory may store the previously determined data in a provisioned section of the cache memory allotted to the image processing circuitry. Additionally, a controller may manage reading and writing of the previously determined data to the provisioned section of the cache memory.

公开(公告)号：US20230064369A1

公开(公告)日：2023-03-02

申请号：US17463292

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit K. Gupta ,  Rohit Natarajan ,  Jurgen M. Schulz ,  Harshavardhan Kaushikkar ,  Connie W. Cheung

IPC: G06F12/0871 ,  G06F12/02 ,  G06F13/16 ,  H03K19/0175

Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

公开(公告)号：US20220084474A1

公开(公告)日：2022-03-17

申请号：US17368522

申请日：2021-07-06

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

公开(公告)号：US20220083486A1

公开(公告)日：2022-03-17

申请号：US17475074

申请日：2021-09-14

Applicant: Apple Inc.

Inventor： Brett D. George ,  Rohit K. Gupta ,  Do Kyung Kim ,  Paul W. Glendenning

IPC: G06F13/28

Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.

公开(公告)号：US20220075440A1

公开(公告)日：2022-03-10

申请号：US17015288

申请日：2020-09-09

Applicant: Apple Inc.

Inventor： Ramana V. Rachakonda ,  Rohit K. Gupta ,  Brad W. Simeral ,  Peter F. Holland

IPC: G06F1/3287 ,  G06F1/3228

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

公开(公告)号：US20230368008A1

公开(公告)日：2023-11-16

申请号：US17745032

申请日：2022-05-16

Applicant: Apple Inc.

Inventor： Sayyed Karen Khatamifard ,  Alexander J. Kirchhoff ,  Rohit K. Gupta ,  Jeffrey D. Marker ,  Thomas G. Anderl ,  Saman Naderiparizi ,  Chenfan Sun ,  Alon Yaakov ,  Husam Khashiboun ,  Ramana V. Rachakonda

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: Embodiments relate to streaming operations in a neural processor circuit that includes a neural engine circuit and a data processor circuit. The neural engine circuit performs first operations on a first input tensor of a first layer to generate a first output tensor, and second operations on a second input tensor of a second layer at a higher hierarchy than the first layer, the second input tensor corresponding to the first output tensor. The data processor circuit stores a portion of the first input tensor for access by the neural engine circuit to perform a subset of the first operations and generate a portion of the first output tensor. The data processor circuit stores the portion of the first output tensor for access by the neural engine circuit as a portion of the second input tensor to perform a subset of the second operations.

公开(公告)号：US11704245B2

公开(公告)日：2023-07-18

申请号：US17462777

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：US20230197022A1

公开(公告)日：2023-06-22

申请号：US18109691

申请日：2023-02-14

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

CPC classification number: G09G3/3426 ,  G09G2320/0646 ,  G09G2360/18 ,  G09G2320/0233 ,  G09G2330/021

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.